TPD12S521 Single-Chip HDMI Transmitter Port Protection and Interface Device
1 Features
- IEC 61000-4-2 Level 4 ESD Protection
- Single-Chip ESD Solution for HDMI Driver
- On-Chip Current Regulator with 55-mA Current Output
- Supports All HDMI 1.3 and HDMI 1.4b Data Rates
(–3 dB Frequency > 3 GHz) - 0.8-pF Capacitance for the High Speed TMDS Lines
- 0.05-pF Matching Capacitance Between the Differential Signal Pair
- 38-Pin TSSOP Provides Seamless Layout Option with HDMI Connector
- Backdrive Protection
- TMDS_D[2:0]+/–
- TMDS_CK+/–
- CE_REMOTE_OUT
- DDC_DAT_OUT
- DDC_CLK_OUT
- HOTPLUG_DET_OUT
- Lead-Free Package
2 Applications
- PCs
- Consumer Electronics
- Set-Top Boxes
- DVD Players
3 Description
The TPD12S521 is a single-chip electro-static discharge (ESD) circuit protection device for the high-definition multimedia interface (HDMI) transmitter port. While providing ESD protection with transient voltage suppression (TVS) diodes, the TVS protection adds little or no additional glitch in the high-speed differential signals. The high-speed transition minimized differential signaling (TMDS) ESD protection lines add only 0.8-pF capacitance.
The low-speed control lines offer voltage-level shifting to eliminate the need for an external voltage level-shifter IC. The control line TVS diodes add 3.5-pF capacitance to the control lines. The 38-pin DBT package offers a seamless layout routing option to eliminate the routing glitch for the differential signal pairs. The DBT package pitch (0.5 mm) matches with the HDMI connector pitch. In addition, the pin mapping follows the same order as the HDMI connector pin mapping. The TPD12S521 provides an on-chip current limiting switch with output ratings of 55 mA at pin 38. This enables HDMI receiver detection even when the receiver device is powered off.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| TPD12S521 | TSSOP (38) | 6.40 mm × 9.70 mm |
- For all available packages, see the orderable addendum at the end of the datasheet.
4 Circuit Protection Scheme
5 Revision History
Changes from E Revision (February 2015) to F Revision
- Add text to Typical ApplicationGo
Changes from D Revision (September 2014) to E Revision
Changes from C Revision (January 2013) to D Revision
- Added Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.Go
6 Pin Configuration and Functions
Pin Functions
| PIN | TYPE | ESD | DESCRIPTION | |
|---|---|---|---|---|
| NAME | NO. | |||
| 5V_SUPPLY | 1 | PWR | 2 kV(1) | Current source for 5V_OUT. |
| LV_SUPPLY | 2 | Bias for CE/DDC/HOTPLUG level shifters. | ||
| GND, TMDS_GND | 3, 5, 8, 11,14, 25, 28, 31, 34, 36 | GND | NA | TMDS ESD and parasitic GND return. |
| TMDS_D2+ | 4, 35 | ESD clamp | 8 kV(2) | TMDS 0.8-pF ESD protection.(3) |
| TMDS_D2– | 6, 33 | |||
| TMDS_D1+ | 7, 32 | |||
| TMDS_D1– | 9, 30 | |||
| TMDS_D0+ | 10, 29 | |||
| TMDS_D0– | 12, 27 | |||
| TMDS_CK+ | 13, 26 | |||
| TMDS_CK– | 15, 24 | |||
| CE_REMOTE_IN | 16 | IO | 2 kV(1) | LV_SUPPLY referenced logic level into ASIC. |
| DDC_CLK_IN | 17 | |||
| DDC_DAT_IN | 18 | |||
| HOTPLUG_DET_IN | 19 | |||
| HOTPLUG_DET_OUT | 20 | IO, ESD clamp | 8 kV(2) | 5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD(4) to connector. |
| DDC_DAT_OUT | 21 | 5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector. | ||
| DDC_CLK_OUT | 22 | |||
| CE_REMOTE_OUT | 23 | IO, ESD clamp | 8 kV(2) | 3.3-V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector. |
| ESD_BYP | 37 | ESD Bypass | 2 kV(1) | ESD bypass. This pin must be connected to a 0.1-µF ceramic capacitor. |
| 5V_OUT | 38 | PWR | 2 kV(1) | 5-V regulator output |