TPS735 低压降 (LDO)、低功耗线性稳压器可提供出色的交流性能以及极低的接地电流。可提供高电源抑制比 (PSRR)、低噪声、快速启动以及出色的线路和负载瞬态响应,同时消耗极低的 45μA(典型值)接地电流。
TPS735 器件与陶瓷电容器搭配使用时可保持稳定,并且该器件使用先进的 BiCMOS 制造工艺,能够在输出 500mA 电流时产生 280mV 的典型压降电压。TPS735 器件使用精密电压基准和反馈环路,可在全部负载、线路、过程和温度变化范围内实现 2% 的总体精度 (VOUT > 2.2V)。此器件的额定 TJ = –40°C 至 +125°C,采用薄型 3mm × 3mm SON-8 封装和 2mm × 2mm WSON-6 封装。
Changes from L Revision (January 2015) to M Revision
Changes from K Revision (August, 2013) to L Revision
Changes from J Revision (May, 2011) to K Revision
Changes from I Revision (April, 2011) to J Revision
Changes from H Revision (November, 2009) to I Revision
Changes from G Revision (March 2009) to H Revision
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | NO | |||
DRV | DRB | |||
IN | 6 | 8 | I | Input supply. A 0.1-µF to 1-µF, low ESR capacitor must be placed from this pin to ground near the device. |
GND | 3 | 4 | — | Ground. The pad must be tied to GND. |
EN | 4 | 5 | I | Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. The EN pin can be connected to the IN pin if not used. |
NR | 2 | 3 | — | This pin is only available for the fixed voltage versions. Connecting an external capacitor to this pin bypasses noise that is generated by the internal band gap and allows the output noise to be reduced to very low levels. The maximum recommended capacitor is 0.01 μF. |
FB | 2 | 3 | I | This pin is only available for the adjustable version. The FB pin is the input to the control-loop error amplifier, and is used to set the output voltage of the device. This pin must not be left floating. |
OUT | 1 | 1 | O | This pin is the output of the regulator. A small, 2.2-μF ceramic capacitor is required from this pin to ground to assure stability. The minimum output capacitance required for stability is 2 µF. |
NC | 5 | 2, 6, 7 | — | Not internally connected. |
Thermal pad | — |