1 Features

• Input Voltage Range: 0.8 V to 5.5 V
• Soft-Start (SS) Pin Provides a Linear Start-Up With Ramp Time Set by External Capacitor
• 1% Accuracy Over Line, Load, and Temperature
• Supports Input Voltages as Low as 0.8 V With External Bias Supply
• Adjustable Output (0.8 V to 3.6 V)
• Ultra-Low Dropout: 55 mV at 1.5 A (Typical)
• Stable With Any or No Output Capacitor
• Excellent Transient Response
• Open-Drain Power-Good (VQFN)
• Active High Enable

2 Applications

• FPGA Applications
• DSP Core and I/O Voltages
• Servers
• Post-Regulation Applications
• Applications With Special Start-Up Time or Sequencing Requirements

3 Description

The TPS742 series of low-dropout (LDO) linear regulators provide an easy-to-use, robust power-management solution for a wide variety of applications. User-programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current on start-up. The soft-start is monotonic and well suited for powering many different types of processors and ASICs. The enable input and power-good output allow easy sequencing with external regulators. This complete flexibility permits the user to configure a solution that meets the sequencing requirements of FPGAs, DSPs, and other applications with special start-up requirements.

A precision reference and error amplifier deliver 1% accuracy over load, line, temperature, and process. Each LDO is stable with low-cost ceramic output capacitors, and the family is fully specified from –40°C to 125°C. The TPS742 devices are offered in a small 5-mm × 5-mm VQFN (RGW) and a small
3.5-mm × 3.5-mm VQFN (RGR) package, yielding a highly compact total solution size. For applications that require additional power dissipation, the DDPAK/TO-263 (KTW) package is also available.

1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Adjustable Output Version

Turnon Response