ZHCSP08 October   2021 ADC09DJ800 , ADC09QJ800 , ADC09SJ800

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 说明（续）
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: DC Specifications
    6. 7.6  Electrical Characteristics: Power Consumption
    7. 7.7  Electrical Characteristics: AC Specifications
    8. 7.8  Timing Requirements
    9. 7.9  Switching Characteristics
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Comparison
      2. 8.3.2 Analog Input
        1. 8.3.2.1 Analog Input Protection
        2. 8.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 8.3.2.3 Analog Input Offset Adjust
        4. 8.3.2.4 ADC Core
          1. 8.3.2.4.1 ADC Theory of Operation
          2. 8.3.2.4.2 ADC Core Calibration
          3. 8.3.2.4.3 Analog Reference Voltage
          4. 8.3.2.4.4 ADC Over-range Detection
          5. 8.3.2.4.5 Code Error Rate (CER)
      3. 8.3.3 Temperature Monitoring Diode
      4. 8.3.4 Timestamp
      5. 8.3.5 Clocking
        1. 8.3.5.1 Converter PLL (C-PLL) for Sampling Clock Generation
        2. 8.3.5.2 LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
        3. 8.3.5.3 Optional CMOS Clock Outputs (ORC, ORD)
        4. 8.3.5.4 SYSREF for JESD204C Subclass-1 Deterministic Latency
          1. 8.3.5.4.1 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          2. 8.3.5.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      6. 8.3.6 JESD204C Interface
        1. 8.3.6.1  Transport Layer
        2. 8.3.6.2  Scrambler
        3. 8.3.6.3  Link Layer
        4. 8.3.6.4  8B/10B Link Layer
          1. 8.3.6.4.1 Data Encoding (8B/10B)
          2. 8.3.6.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 8.3.6.4.3 Code Group Synchronization (CGS)
          4. 8.3.6.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 8.3.6.4.5 Frame and Multiframe Monitoring
        5. 8.3.6.5  64B/66B Link Layer
          1. 8.3.6.5.1 64B/66B Encoding
          2. 8.3.6.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
            1. 8.3.6.5.2.1 Block, Multiblock and Extended Multiblock Alignment using Sync Header
              1. 8.3.6.5.2.1.1 Cyclic Redundancy Check (CRC) Mode
              2. 8.3.6.5.2.1.2 Forward Error Correction (FEC) Mode
          3. 8.3.6.5.3 Initial Lane Alignment
          4. 8.3.6.5.4 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 8.3.6.6  Physical Layer
          1. 8.3.6.6.1 SerDes Pre-Emphasis
        7. 8.3.6.7  JESD204C Enable
        8. 8.3.6.8  Multi-Device Synchronization and Deterministic Latency
        9. 8.3.6.9  Operation in Subclass 0 Systems
        10. 8.3.6.10 Alarm Monitoring
          1. 8.3.6.10.1 Clock Upset Detection
          2. 8.3.6.10.2 FIFO Upset Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Power Mode and High Performance Mode
      2. 8.4.2 JESD204C Modes
        1. 8.4.2.1 JESD204C Transport Layer Data Formats
        2. 8.4.2.2 64B/66B Sync Header Stream Configuration
        3. 8.4.2.3 Redundant Data Mode (Alternate Lanes)
      3. 8.4.3 Power-Down Modes
      4. 8.4.4 Test Modes
        1. 8.4.4.1 Serializer Test-Mode Details
        2. 8.4.4.2 PRBS Test Modes
        3. 8.4.4.3 Clock Pattern Mode
        4. 8.4.4.4 Ramp Test Mode
        5. 8.4.4.5 Short and Long Transport Test Mode
          1. 8.4.4.5.1 Short Transport Test Pattern
        6. 8.4.4.6 D21.5 Test Mode
        7. 8.4.4.7 K28.5 Test Mode
        8. 8.4.4.8 Repeated ILA Test Mode
        9. 8.4.4.9 Modified RPAT Test Mode
      5. 8.4.5 Calibration Modes and Trimming
        1. 8.4.5.1 Foreground Calibration Mode
        2. 8.4.5.2 Background Calibration Mode
        3. 8.4.5.3 Low-Power Background Calibration (LPBG) Mode
      6. 8.4.6 Offset Calibration
      7. 8.4.7 Trimming
    5. 8.5 Programming
      1. 8.5.1 Using the Serial Interface
      2. 8.5.2 SCS
      3. 8.5.3 SCLK
      4. 8.5.4 SDI
      5. 8.5.5 SDO
      6. 8.5.6 Streaming Mode
      7. 8.5.7 SPI_Register_Map Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Analog Front-End Requirements
          2. 9.2.1.2.2 Calculating Clock and SerDes Frequencies
        3. 9.2.1.3 Application Curves
    3. 9.3 Initialization Set Up
  10. 10Power Supply Recommendations
    1. 10.1 Power Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

1 特性

  • ADC 内核：
    • 分辨率：9 位
    • 非交错式架构
    • 内部抖动可减少高次谐波
  • 性能规格：
    • SNR（–1dBFS，97MHz）：53.5dBFS
    • ENOB（–1dBFS，97MHz）：8.51 位
    • SFDR（–1dBFS，97MHz）：64dBFS
    • 本底噪声（–20dBFS，97MHz）；-140.5dBFS/Hz
  • 满量程输入电压：800mVPP-DIFF
  • 全功率输入带宽：6GHz
  • JESD204C 串行数据接口：
    • 总共支持 2 至 8 个（四通道/双通道）或 1 至 4 个（单通道）串行器/解串器通道
    • 最大波特率：17.16Gbps
    • 64B/66B 和 8B/10B 编码模式
    • 子类 1 支持确定性延迟
    • 与 JESD204B 接收器兼容
  • 可选的内部采样时钟生成
    • 内部 PLL 和 VCO (7.2–8.2GHz)
  • SYSREF 窗口可简化同步
  • 四个时钟输出可简化系统时钟
    • FPGA 或相邻 ADC 的参考时钟
    • 串行器/解串器收发器的参考时钟
  • 脉冲系统的时间戳输入和输出
  • 功耗 (800MSPS)：
    • 四通道：每通道 420mW
    • 双通道：每通道 555mW
    • 单通道：840mW
  • 电源：1.1V/1.9V
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