1 Features

• ADS41B49: 14-Bit, 250 MSPS
  ADS41B29: 12-Bit, 250 MSPS
• Integrated High-Impedance
  Analog Input Buffer:
  • Input Capacitance: 2 pF
  • 200-MHz Input Resistance: 3 kΩ
• Maximum Sample Rate: 250 MSPS
• Ultralow Power:
  • 1.8-V Analog Power: 180 mW
  • 3.3-V Buffer Power: 96 mW
  • I/O Power: 135 mW (DDR LVDS)
• High Dynamic Performance:
  • SNR: 69 dBFS at 170 MHz
  • SFDR: 82.5 dBc at 170 MHz
• Output Interface:
  • Double Data Rate (DDR) LVDS with Programmable Swing and Strength:
    • Standard Swing: 350 mV
    • Low Swing: 200 mV
    • Default Strength: 100-Ω Termination
    • 2x Strength: 50-Ω Termination
  • 1.8-V Parallel CMOS Interface Also Supported
• Programmable Gain for SNR, SFDR Trade-Off
• DC Offset Correction
• Supports Low Input Clock Amplitude
• Package: VQFN-48 (7 mm × 7 mm)

2 Applications

• Power Amplifier Linearization
• Software Defined Radio
• Wireless Communications Infrastructure

3 Description

The ADS41Bx9 are members of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. These devices use innovative design techniques to achieve high dynamic performance, and consume extremely low power. The analog input pins have buffers, with benefits of constant performance and input impedance across a wide frequency range. The devices are well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization.

The ADS41Bx9 have features such as digital gain and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.

The devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500 MBPS) makes using low-cost field-programmable gate array (FPGA)-based receivers possible. The devices have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50-Ω differential termination.

1. For all available packages, see the orderable addendum at the end of the data sheet.

ADS41B49 Block Diagram

4 Revision History

Changes from E Revision (July 2012) to F Revision

• Changed title and changed ADS41B49/29 to ADS41Bx9 and QFN to VQFN throughout documentGo
• Added Applications section, Device Information table, front-page figure, ESD Ratings table, Feature Description section, Device Functional Modes section, Programming section, Register Maps section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo
• Deleted Ordering Information table Go
• Changed Pin Functions table: changed title and format Go
• Added Added last row to Voltage applied to input pins section in Absolute Maximum Ratings tableGo
• Changed Temperature parameters in Absolute Maximum Ratings table: changed format of Temperature section and changed maximum specifications for T_A and T_JGo
• Changed TYP column header to NOM in Recommended Operating Conditions tableGo
• Changed Digital Outputs, T_J parameter in Recommended Operating Conditions tableGo
• Deleted High-Performance Modes section from Recommended Operating Conditions tableGo
• Changed conditions of Electrical Characteristics: General table from temperature to ambient temperatureGo
• Changed conditions of Electrical Characteristics: ADS41B29, ADS41B49 table from temperature to ambient temperatureGo
• Added footnote 1 to Electrical Characteristics: ADS41B29, ADS41B49 tableGo
• Changed conditions of Timing Requirements: LVDS and CMOS Modes table from temperature to ambient temperatureGo
• Added footnotes 6 and 7 to Timing Requirements: LVDS and CMOS Modes tableGo
• Added footnote 1 to Timing Requirements: Reset table Go
• Changed title of Figure 13 and Figure 14 Go
• Changed title of Figure 31 and Figure 32 Go
• Changed conditions of Table 6 Go
• Added Summary of High-Performance Modes sectionGo
• Changed bit registers to satisfy new standard requirements Go

Changes from D Revision (December 2010) to E Revision

• Updated Thermal Information table valuesGo
• Changed Analog Inputs, Differential input capacitance parameter typical specification in Electrical Characteristics: General tableGo
• Changed value of input capacitance in Analog Input sectionGo
• Updated Figure 54 and footnotesGo
• Changed register 25h default value in Table 7Go
• Changed register 42 default and bit D3 values in Table 7Go
• Changed default value for Register Address 25hGo
• Changed default and bit 3 values for Register Address 42hGo
• Updated Figure 83Go
• Updated Figure 84Go