1 Features

• 2:4 Differential Buffer
• Low Additive Jitter: <300 fs RMS in 10-kHz to
  20-MHz
• Low Output Skew of 20 ps (Maximum)
• Universal Inputs Accept LVDS, LVPECL, and LVCMOS
• Selectable Clock Inputs Through Control Pin
• 4 LVDS Outputs, ANSI EAI/TIA-644A Standard Compatible
• Clock Frequency: Up to 800 MHz
• Device Power Supply: 2.375 V to 2.625 V
• LVDS Reference Voltage, V_{AC_REF}, Available for Capacitive Coupled Inputs
• Industrial Temperature Range: –40°C to 85°C
• Packaged in 3 mm × 3 mm, 16-Pin VQFN (RGT)
• ESD Protection Exceeds 3 kV HBM, 1 kV CDM

2 Applications

• Telecommunications and Networking
• Medical Imaging
• Test and Measurement Equipment
• Wireless Communications
• General Purpose Clocking

3 Description

The CDCLVD1204 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through OUT3) with minimum skew for clock distribution. The CDCLVD1204 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD1204 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage, V_{AC_REF}, must be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static). The part supports a fail safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 2.5-V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1204 is packaged in small, 16-pin, 3-mm × 3-mm VQFN package.

1. For all available packages, see the orderable addendum at the end of the data sheet.

Application Example