The DAC121S101QML-SP device is a full-featured, general-purpose, 12-bit voltage-output digital-to-analog converter (DAC) that can operate from a single 2.7-V to 5.5-V supply and consumes just
177 µA of current at 3.6 V. The on-chip output amplifier allows rail-to-rail output swing and the three-wire serial interface operates at clock rates up to
20 MHz over the specified supply voltage range and is compatible with standard SPI, QSPI, MICROWIRE, and DSP interfaces.
The supply voltage for the DAC121S101QML-SP serves as its voltage reference, providing the widest possible output dynamic range. A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a valid write to the device. A power-down feature reduces power consumption to less than a microWatt.
The low power consumption and small packages of the DAC121S101QML-SP make it an excellent choice for use in battery-operated equipment.
PART NUMBER | GRADE | PACKAGE |
---|---|---|
DAC121S101WGRQV | 5962R0722601VZA 100 krad | 10-lead ceramic SOIC |
DAC121S101WGRLV | 5962R0722602VZA 100 krad ELDRS-Free | 10-lead ceramic SOIC |
DAC121S101-MDR | 5962R0722601V9A 100 krad | Die |
DAC121S101WGMPR | Pre-Flight Engineering Prototype | 10-lead ceramic SOIC |
DAC121S101CVAL | Ceramic Evaluation Board | 10-lead ceramic SOIC |
Changes from E Revision (March 2013) to F Revision
Changes from D Revision (March 2013) to E Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | VA | — | Power supply and reference input; must be decoupled to GND |
2 | N/C | — | No connect; pin not internally connected to die |
3 | N/C | — | No connect; pin not internally connected to die |
4 | VOUT | Output | DAC analog output voltage |
5 | N/C | — | No connect; pin not internally connected to die |
6 | N/C | — | No connect; pin not internally connected to die |
7 | SYNC | Input | Frame synchronization input for the data input. When this pin goes low, it enables the input shift register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. |
8 | SCLK | Input | Serial clock input; data is clocked into the input shift register on the falling edges of this pin. |
9 | DIN | Input | Serial data input; data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC. |
10 | GND | — | Ground reference for all on-chip circuitry |