DATA SHEET
DAC8551-Q1 汽车类 16 位、超低毛刺脉冲、电压输出 DAC
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1 特性
- 适用于汽车电子 应用
- 具有符合 AEC-Q100 的下列结果：
- 器件温度 1 级：-40°C 至 125°C 的环境运行温度范围
- 器件人体放电模式 (HBM) 静电放电 (ESD) 分类等级 2
- 器件组件充电模式 (CDM) ESD 分类等级 C4B
- 相对精度：16 最低有效位 (LSB) 积分非线性 (INL)
- 超低毛刺脉冲：0.1nV-s
- 稳定时间：8μs 达到 ±0.003% 满量程范围 (FSR)
- 电源：3.2V 至 5.5V
- 上电复位为零量程
- 微功耗运行：5V 时为 160μA
- 具有施密特触发输入的低功耗串口
- 支持轨至轨运行的片上输出缓冲放大器
- 掉电能力
- 二进制输入
- SYNC 中断功能
- 采用微型超薄小外形尺寸封装 (VSSOP)-8 封装
2 应用
- 汽车雷达
- 车用传感器
3 说明
DAC8551-Q1 是一款小型、低功耗、电压输出、16 位数模转换器 (DAC)，符合汽车类 应用的需求。DAC8551-Q1 具有出色的线性度，并且最大限度减少了意外的码间瞬态电压。DAC8551-Q1 器件采用时钟速率达 30MHz 的通用三线制串口，并且兼容标准的 SPI、QSPI、Microwire 和数字信号处理器 (DSP) 接口。
DAC8551-Q1 需要使用一个外部基准电压来设置其输出范围。DAC8551-Q1 包含一个上电复位电路，可确保 DAC 输出在 0V 时上电，并在器件被执行有效写操作之前一直保持此状态。DAC8551-Q1 包含一个由串口访问的掉电特性，可将器件在 5V 电压下的电流消耗降低至 800μA。
DAC8551-Q1 在 5V 电压下的功耗仅为 800µW，在掉电模式下的功耗降至 4μW 以下。DAC8551-Q1 采用 VSSOP-8 封装。
Table 1. 器件信息(1)
| 器件型号 | 封装 | 封装尺寸（标称值） |
|---|---|---|
| DAC8551-Q1 | 超薄小外形尺寸封装 (VSSOP) (8) | 3.00mm × 3.00mm |
- 要了解所有可用封装，请见数据表末尾的可订购米6体育平台手机版_好二三四附录。
5 Pin Configuration and Functions
DGK Package
8-Pin VSSOP
Top View
Table 2. Pin Functions
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| DIN | 7 | I | Serial data input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock input. Schmitt-trigger logic input. |
| GND | 8 | GND | Ground reference point for all circuitry on the device |
| SCLK | 6 | I | Serial clock input. Data can be transferred at rates up to 3 0MHz. Schmitt-trigger logic input. |
| SYNC | 5 | I | Level-triggered control input (active-low). This is the frame synchronization signal for the input data. SYNC going low enables the input shift register, and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock (unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC8551-Q1). Schmitt-trigger logic input. |
| VDD | 1 | PWR | Power supply input, 3.2 V to 5.5 V. |
| VFB | 3 | I | Feedback connection for the output amplifier. For voltage output operation, tie to VOUT externally. |
| VOUT | 4 | O | Analog output voltage from DAC. The output amplifier has rail-to-rail operation. |
| VREF | 2 | I | Reference voltage input. |
6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| VDD to GND | –0.3 | 6 | V | |
| Digital input voltage to GND | DIN, SCLK and SYNC | –0.3 | VDD + 0.3 | V |
| VOUT to GND | –0.3 | VDD + 0.3 | V | |
| VREF to GND | –0.3 | VDD + 0.3 | V | |
| VFB to GND | –0.3 | VDD + 0.3 | V | |
| Junction temperature range, TJ max | –65 | 150 | °C | |
| Storage temperature, Tstg | –65 | 150 | °C | |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
| VALUE | UNIT | ||||
|---|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | ±2000 | V | |
| Charged-device model (CDM), per AEC Q100-011 | All pins | ±500 | |||
| Corner pins (1, 4, 5, and 8) | ±750 | ||||
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| POWER SUPPLY | ||||||
| Supply voltage | VDD to GND | 3.2 | 5.5 | V | ||
| DIGITAL INPUTS | ||||||
| Digital input voltage | DIN, SCLK and SYNC | 0 | VDD | V | ||
| REFERENCE INPUT | ||||||
| VREF | Reference input voltage | 0 | VDD | V | ||
| AMPLIFIER FEEDBACK INPUT | ||||||
| VFB | Output amplifier feedback input | VOUT | V | |||
| TEMPERATURE RANGE | ||||||
| TA | Operating ambient temperature | –40 | 125 | °C | ||
6.4 Thermal Information
| THERMAL METRIC(1) | DAC8551-Q1 | UNIT | |
|---|---|---|---|
| DGK (VSSOP) | |||
| 8 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 173.7 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 94.2 | °C/W |
| RθJB | Junction-to-board thermal resistance | 65.4 | °C/W |
| ψJT | Junction-to-top characterization parameter | 10.2 | °C/W |
| ψJB | Junction-to-board characterization parameter | 92.7 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
VDD = 3.2 V to 5.5 V, VREF = VDD and TA = –40°C to 125°C, unless otherwise noted.| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| STATIC PERFORMANCE(1) | |||||||
| Resolution | 16 | Bits | |||||
| Relative accuracy | ±4 | ±16 | LSB | ||||
| Differential nonlinearity | ±0.35 | ±2 | LSB | ||||
| Offset error | ±1 | ±15 | mV | ||||
| Full-scale error | ±0.05 | ±0.5 | % of FSR | ||||
| Gain error | ±0.02 | ±0.2 | % of FSR | ||||
| Offset error drift | ±5 | μV/°C | |||||
| Gain temperature coefficient | ±1 | ppm of FSR/°C | |||||
| PSRR | Power-supply rejection ratio | RL = 2 kΩ, CL = 200 pF | 0.75 | mV/V | |||
| OUTPUT CHARACTERISTICS(2) | |||||||
| Output voltage range | 0 | VREF | V | ||||
| Output voltage settling time | To ±0.003% FSR, 0200h to FD00h RL = 2 kΩ, 0 pF < CL < 200 pF |
8 | μs | ||||
| Slew rate | 1.4 | V/μs | |||||
| Capacitive load stability | RL = ∞ | 470 | pF | ||||
| RL = 2 kΩ | 1000 | pF | |||||
| Code change glitch impulse | 1 LSB change around major carry | 0.1 | nV-s | ||||
| Digital feedthrough | 50 kΩ series resistance on digital lines | 0.1 | nV-s | ||||
| DC output impedance | At mid-code input | 1 | Ω | ||||
| Short-circuit current | VDD = 3.2 V to 5.5 V | 35 | mA | ||||
| AC PERFORMANCE | |||||||
| SNR | Signal-to-noise ratio | BW = 20 kHz, VDD = 5 V, VREF = 4.5 V, fOUT = 1 kHz First 19 harmonics removed for SNR calculation |
84 | dB | |||
| THD | Total harmonic distortion | –80 | dB | ||||
| SFDR | Spurious-free dynamic range | 84 | dB | ||||
| SINAD | Signal to noise and distortion | 76 | dB | ||||
| REFERENCE INPUT | |||||||
| Reference current | VREF = VDD = 5.5 V | 50 | μA | ||||
| VREF = VDD = 3.6 V | 25 | ||||||
| Reference input range | 0 | VDD | V | ||||
| Reference input impedance | 125 | kΩ | |||||
| LOGIC INPUTS(2) | |||||||
| Input current | ±1 | μA | |||||
| VINL | Input low voltage | VDD = 5 V | 0.3×VDD | V | |||
| VDD = 3.3 V | 0.1×VDD | ||||||
| VINH | Input high voltage | VDD = 5 V | 0.7×VDD | V | |||
| VDD = 3.3 V | 0.9×VDD | ||||||
| Pin capacitance | 3 | pF | |||||
| POWER REQUIREMENTS | |||||||
| VDD | Supply voltage | 3.2 | 5.5 | V | |||
| IDD | Supply current | Normal mode, input code = 32,768, no load, does not include reference current. VIH = VDD and VIL = GND, VDD = 3.6 V to 5.5 V |
160 | 250 | μA | ||
| Normal mode, input code = 32,768, no load, does not include reference current. VIH = VDD and VIL = GND, VDD = 3.2 V to 3.6 V |
110 | 240 | |||||
| All power-down modes, VIH = VDD and VIL = GND, VDD = 3.6 V to 5.5 V |
0.8 | 3 | |||||
| All power-down modes, VIH = VDD and VIL = GND, VDD = 3.2 V to 3.6 V |
0.5 | 3 | |||||
| POWER EFFICIENCY | |||||||
| IOUT / IDD | ILOAD = 2 mA, VDD = 5 V | 89% | |||||
| TEMPERATURE RANGE | |||||||
| TA | Ambient temperature | –40 | 125 | °C | |||
(1) Linearity calculated using a reduced code range of 485 to 64,741; output unloaded.
(2) Specified by design and characterization; not production tested.
6.6 Timing Requirements(1)(2)
VDD = 3.2 V to 5.5 V and TA = –40°C to 125°C, unless otherwise noted.| PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
|---|---|---|---|---|---|---|
| fSCLK | Serial clock frequency | VDD = 3.2 V to 3.6 V | 25 | MHz | ||
| VDD = 3.6 V to 5.5 V | 30 | |||||
| t1 | SCLK cycle time | VDD = 3.2 V to 3.6 V | 40 | ns | ||
| VDD = 3.6 V to 5.5 V | 34 | |||||
| t2 | SCLK high time | VDD = 3.2 V to 3.6 V | 13 | ns | ||
| VDD = 3.6 V to 5.5 V | 13 | |||||
| t3 | SCLK low time | VDD = 3.2 V to 3.6 V | 22.5 | ns | ||
| VDD = 3.6 V to 5.5 V | 13 | |||||
| t4 | SYNC to SCLK rising edge setup time | VDD = 3.2 V to 3.6 V | 0 | ns | ||
| VDD = 3.6 V to 5.5 V | 0 | |||||
| t5 | Data setup time | VDD = 3.2 V to 3.6 V | 5 | ns | ||
| VDD = 3.6 V to 5.5 V | 5 | |||||
| t6 | Data hold time | VDD = 3.2 V to 3.6 V | 5 | ns | ||
| VDD = 3.6 V to 5.5 V | 5 | |||||
| t7 | 24th SCLK falling edge to SYNC rising edge | VDD = 3.2 V to 3.6 V | 0 | ns | ||
| VDD = 3.6 V to 5.5 V | 0 | |||||
| t8 | Minimum SYNC high time | VDD = 3.2 V to 3.6 V | 50 | ns | ||
| VDD = 3.6 V to 5.5 V | 34 | |||||
| t9 | 24th SCLK falling edge to SYNC falling edge | VDD = 3.2 V to 5.5 V | 50 | ns | ||
(1) All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH) / 2.
(2) See the Serial-Write-Operation Timing Diagram.
6.7 Switching Characteristics
over operating ambient temperature range (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| Power-up time | Coming out of power-down mode, VDD = 5 V | 2.5 | µs | |||
| Coming out of power-down mode, VDD = 3.3 V | 5 | |||||
Figure 1. Serial-Write-Operation Timing Diagram
6.8 Typical Characteristics
At TA = 25°C, VDD = 5 V unless otherwise noted.
Figure 2. Linearity Error and Differential Linearity Error vs Digital Input Code (–40°C)
Figure 4. Linearity Error and Differential Linearity Error vs Digital Input Code (125°C)
Figure 6. Full-Scale Error vs Temperature
Figure 8. Supply Current vs Digital Input Code
Figure 10. Supply Current vs Supply Voltage
Figure 12. Supply Current vs Logic Input Voltage
Figure 14. Full-Scale Settling Time: 5-V Falling Edge
Figure 16. Half-Scale Settling Time: 5-V Falling Edge
Figure 18. Glitch Impulse: 5 V, 1-LSB Step, Falling Edge
Figure 20. Glitch Impulse: 5 V, 16-LSB Step, Falling Edge
Figure 22. Glitch Impulse: 5 V, 256-LSB Step, Falling Edge
Figure 24. Signal-to-Noise Ratio vs Output Frequency
Figure 26. Output Noise Density
Figure 3. Linearity Error and Differential Linearity Error vs Digital Input Code (25°C)
Figure 5. Offset Error vs Temperature
Figure 7. Source and Sink Current Capability
Figure 9. Power-Supply Current vs Temperature
Figure 11. Power-Down Current vs Supply Voltage
Figure 13. Full-Scale Settling Time: 5-V Rising Edge
Figure 15. Half-Scale Settling Time: 5-V Rising Edge
Figure 17. Glitch Impulse: 5 V, 1-LSB Step, Rising Edge
Figure 19. Glitch Impulse: 5 V, 16-LSB Step, Rising Edge
Figure 21. Glitch Impulse: 5 V, 256-LSB Step, Rising Edge
Figure 23. Total Harmonic Distortion vs Output Frequency
Figure 25. Power Spectral Density