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DP83848x PHYTER Mini / LS Single Port 10/100 MB/s Ethernet Transceiver
SNLS250E
May 2008 – April 2015
DP83848H
,
DP83848J
,
DP83848K
,
DP83848M
,
DP83848T
PRODUCTION DATA.
CONTENTS
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DP83848x PHYTER Mini / LS Single Port 10/100 MB/s Ethernet Transceiver
1
Device Overview
1.1
Features
1.2
Applications
1.3
Description
1.4
Functional Block Diagram
2
Revision History
3
Device Comparison
4
Pin Configuration and Functions
4.1
Pin Diagram
4.2
Package Pin Assignments
4.3
Serial Management Interface
4.4
Mac Data Interface
4.5
Clock Interface
4.6
LED Interface
4.7
Reset
4.8
Strap Options
4.9
10 Mb/s and 100 Mb/s PMD Interface
4.10
Special Connections
4.11
Power Supply Pins
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
DC Specifications
5.6
AC Timing Requirements
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Auto-Negotiation
6.3.1.1
Auto-Negotiation Pin Control
6.3.1.2
Auto-Negotiation Register Control
6.3.1.3
Auto-Negotiation Parallel Detection
6.3.1.4
Auto-Negotiaion Restart
6.3.1.5
Auto-Negotiation Complete Time
6.3.2
Auto-MDIX
6.3.3
LED Interface
6.3.3.1
LED
6.3.3.2
LED Direct Control
6.3.4
Internal Loopback
6.3.5
BIST
6.3.6
Energy Detect Mode
6.4
Device Functional Modes
6.4.1
MII Interface
6.4.1.1
Nibble-wide MII Data Interface
6.4.1.2
Collision Detect
6.4.1.3
Carrier Sense
6.4.2
Reduced MII Interface
6.4.3
802.3 MII Serial Management Interface
6.4.3.1
Serial Management Register Access
6.4.3.2
Serial Management Access Protocol
6.4.3.3
Serial Management Preamble Suppression
6.4.4
PHY Address
6.4.4.1
MII Isolate Mode
6.4.5
Half Duplex vs Full Duplex
6.4.6
Reset Operation
6.4.6.1
Hardware Reset
6.4.6.2
Software Reset
6.4.7
Power Down
6.5
Programming
6.5.1
Architecture
6.5.1.1
100BASE-TX Transmitter
6.5.1.1.1
Code-Group Encoding and Injection
6.5.1.1.2
Scrambler
6.5.1.1.3
NRZ to NRZI Encoder
6.5.1.1.4
Binary to MLT-3 Convertor
6.5.1.2
100BASE-TX Receiver
6.5.1.2.1
Analog Front End
6.5.1.2.2
Digital Signal Processor
6.5.1.2.3
Digital Adaptive Equalization and Gain Control
6.5.1.2.4
Base Line Wander Compensation
6.5.1.2.5
Signal Detect
6.5.1.2.6
MLT-3 to NRZI Decoder
6.5.1.2.7
NRZI to NRZ
6.5.1.2.8
Serial to Parallel
6.5.1.2.9
Descrambler
6.5.1.2.10
Code-Group Alignment
6.5.1.2.11
4B/5B Decoder
6.5.1.2.12
100BASE-TX Link Integrity Monitor
6.5.1.2.13
Bad SSD Detection
6.5.1.3
10BASE-T Transceiver Module
6.5.1.3.1
Operational Modes
6.5.1.3.2
Smart Squelch
6.5.1.3.3
Collision Detection and SQE
6.5.1.3.4
Carrier Sense
6.5.1.3.5
Normal Link Pulse Detection/Generation
6.5.1.3.6
Jabber Function
6.5.1.3.7
Automatic Link Polarity Detection and Correction
6.5.1.3.8
Transmit and Receive Filtering
6.5.1.3.9
Transmitter
6.5.1.3.10
Receiver
6.6
Memory
6.6.1
Register Block
6.6.1.1
Register Definition
6.6.1.1.1
Basic Mode Control Register (BMCR)
6.6.1.1.2
Basic Mode Status Register (BMSR)
6.6.1.1.3
PHY Identifier Register #1 (PHYIDR1)
6.6.1.1.4
PHY Identifier Register #2 (PHYIDR2)
6.6.1.1.5
Auto-Negotiation Advertisement Register (ANAR)
6.6.1.1.6
Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
6.6.1.1.7
Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page)
6.6.1.1.8
Auto-Negotiate Expansion Register (ANER)
6.6.1.1.9
Auto-Negotiation Next Page Transmit Register (ANNPTR)
6.6.1.2
Extended Registers
6.6.1.2.1
PHY Status Register (PHYSTS)
6.6.1.2.2
False Carrier Sense Counter Register (FCSCR)
6.6.1.2.3
Receiver Error Counter Register (RECR)
6.6.1.2.4
100 Mb/s PCS Configuration and Status Register (PCSR)
6.6.1.2.5
RMII and Bypass Register (RBR)
6.6.1.2.6
LED Direct Control Register (LEDCR)
6.6.1.2.7
PHY Control Register (PHYCR)
6.6.1.2.8
10BASE-T Status/Control Register (10BTSCR)
6.6.1.2.9
CD Test and BIST Extensions Register (CDCTRL1)
6.6.1.2.10
Energy Detect Control (EDCR)
7
Application, Implementation, and Layout
7.1
Application Information
7.2
Typical Application
7.2.1
Design Requirements
7.2.1.1
TPI Network Circuit
7.2.1.2
Clock IN (X1) Recommendations
7.2.1.2.1
Oscillator
7.2.1.2.2
Crystal
7.2.1.3
Power Feedback Circuit
7.2.1.4
Magnetics
7.2.2
Detailed Design Procedure
7.2.2.1
MAC Interface (MII/RMII)
7.2.2.1.1
Termination Requirement
7.2.2.1.2
Recommended Maximum Trace Length
7.2.2.2
Calculating Impedance
7.2.2.2.1
Microstrip Impedance - Single-Ended
7.2.2.2.2
Stripline Impedance - Single-Ended
7.2.2.2.3
Microstrip Impedance - Differential
7.2.2.2.4
Stripline Impedance - Differential
7.2.3
Application Curves
7.3
Layout
7.3.1
Layout Guidelines
7.3.1.1
PCB Layer Stacking
7.3.2
Layout Example
7.4
Power Supply Recommendations
8
Device and Documentation Support
8.1
Documentation Support
8.1.1
Related Documentation
8.2
Related Links
8.3
Trademarks
8.4
Electrostatic Discharge Caution
8.5
Glossary
9
Mechanical Packaging and Orderable Information
IMPORTANT NOTICE
封装选项
机械数据 (封装 | 引脚)
RTA|40
MPQF134A
散热焊盘机械数据 (封装 | 引脚)
RTA|40
QFND447B
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