1 Features

• >400 Mbps (200 MHz) Switching Rates
• 0.1-ns Channel-to-Channel Skew (Typical)
• 0.1-ns Differential Skew (Typical)
• 3.3-ns Maximum Propagation Delay
• 3.3-V Power Supply Design
• Power Down High Impedance on LVDS Inputs
• Low Power Design (40 mW at 3.3 V Static)
• Interoperable With Existing 5-V LVDS Networks
• Accepts Small Swing (350 mV Typical) VID
• Supports Open, Short, and Terminated Input Fail-Safe
• Compatible With ANSI/TIA/EIA-644
• Industrial Temperature Operating Range (–40°C to 85°C)
• Available in SOIC and TSSOP Packaging

2 Applications

• Building And Factory Automation
• Grid Infrastructure

3 Description

The DS90LV032A is a quad CMOS differential line receiver designed for applications requiring ultra-low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) using Low Voltage Differential Signaling (LVDS) technology.

The DS90LV032A accepts low voltage (350 mV typical) differential input signals and translates them to 3-V CMOS output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports open, shorted, and terminated (100 Ω) input Fail-safe. The receiver output is HIGH for all fail-safe conditions.

The DS90LV032A and companion LVDS line driver (for example, DS90LV031A) provide a new alternative to high power PECL or ECL devices for high speed point-to-point interface applications.

1. For all available packages, see the orderable addendum at the end of the data sheet.

Block Diagram