CDCM7005-SP 3.3-V High Performance Rad-Tolerant Class V, Clock Synchronizer and Jitter Cleaner
- SGLS390G July 2009 – November 2015 CDCM7005-SP
  
  PRODUCTION DATA.

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DATA SHEET

CDCM7005-SP 3.3-V High Performance Rad-Tolerant Class V, Clock Synchronizer and Jitter Cleaner

1 Features

High Performance LVPECL and LVCMOS PLL Clock Synchronizer
Two Reference Clock Inputs (Primary and Secondary Clock) for Redundancy Support With Manual or Automatic Selection
Accepts LVCMOS Input Frequencies Up to
200 MHz
VCXO_IN Clock is Synchronized to One of the Two Reference Clocks
VCXO_IN Frequencies Up to 2 GHz (LVPECL)
Outputs can be a Combination of LVPECL and LVCMOS (Up to Five Differential LVPECL Outputs or Up to 10 LVCMOS Outputs)
Output Frequency is Selectable by x1, /2, /3, /4, /6, /8, /16 on Each Output Individually
Efficient Jitter Cleaning from Low PLL Loop Bandwidth
Low Phase Noise PLL Core
Programmable Phase Offset (PRI_REF and SEC_REF to Outputs)
Wide Charge Pump Current Range From
200 μA to 3 mA
Analog and Digital PLL Lock Indication
Provides VBB Bias Voltage Output for Single-Ended Input Signals (VCXO_IN)
Frequency Hold Over Mode Improves Fail-Safe Operation
Power-Up Control Forces LVPECL Outputs to Tri-State at V_CC < 1.5 V
SPI Controllable Device Setting
3.3-V Power Supply
High-Performance 52 Pin Ceramic Quad Flat Pack (HFG)
Rad-Tolerant : 50 kRad (Si) TID
QML-V Qualified, SMD 5962-07230
Military Temperature Range: –55°C to 125°C T_case
Engineering Evaluation (/EM) Samples are Available ⁽¹⁾

⁽¹⁾

(1)These units are intended for engineering evaluation only. They are processed to a non-compliant flow (for example, no burn-in, and so forth) and are tested to temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance on full MIL specified temperature range of –55°C to 125°C or operating life.

2 Applications

Low-Jitter Clock Distribution
SERDES Links
Analog Data Converters
Digital-to-Analog Converters

3 Description

The CDCM7005-SP is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O as VC(X)O_IN / PRI_REF = (N × P) / M or VC(X)O_IN / SEC_REF = (N × P) / M.

VC(X)O_IN clock operates up to 2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
CDCM7005-SP	CFP (52)	13.97 mm × 13.97 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Schematic

4 Revision History

Changes from F Revision (January 2014) to G Revision

Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
Deleted two bullets from the Features List. Go

Changes from E Revision (August 2012) to F Revision

Added /EM bullet to FeaturesGo
Deleted Ordering Information tableGo

Changes from D Revision (December 2011) to E Revision

Changed PLL_LOCK pin description, replaced cycle-slip text.Go
Changed the Frequency Hold-Over Mode sectionGo
Changed text From: Cycle-Slip To: Frequency Offset in Figure 22Go
Changed table Word 3, Cycle Slip (Bit 6) To: Frequency OffsetGo
Changed Note 1 of table Word 3Go
Changed table Lock-Detect Window (Word 3) - Clip slip To: Frequency offset, and Note 2Go

Changes from B Revision (December 2009) to C Revision

Changed the VCC pin text - From: There is no internal connection between V_CC and AV_CC To: V_CC and AV_CC should always have same supply voltageGo
Added to the CTRL_LE - Unused or floating inputs must be tied to proper logic level. It is recommended to use a 20-kΩ or larger pullup resistor to VCCGo
Added to the CTRL_CLK pin - Unused or floating inputs must be tied to proper logic level. It is recommended to use a 20-kΩ or larger pullup resistor to VCCGo
Added to the CTRL_DATA pin - Unused or floating inputs must be tied to proper logic level. It is recommended to use a 20-kΩ or larger pullup resistor to VCCGo
Added to the PD pin text - It is recommended to ramp up the...Go
Added to the SPI CONTROL INTERFACE section - Unused or floating inputs must be tied to proper logic level. It is recommended to use a 20-kΩ or larger pullup resistor to VCCGo
Added to the SPI CONTROL INTERFACE section - It is recommended to program Word 0, Word 1, Word 2 and Word 3 right after power up and PD becomes HIGHGo
Changed bit 16 from RES to GTMEGo
Changed bit 28 from RES to PFDFCGo

5 Description (continued)

The CDCM7005-SP can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005-SP are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The LVCMOS outputs are arranged in pairs (Y0A:Y0B, Y1A:Y1B, …), so that each pair has the same frequency. But each output can be separately inverted and disabled. The built in synchronization latches ensure that all outputs are synchronized for low output skew.

All device settings, like outputs signaling, divider value, input selection, and many more, are programmable by SPI (3-wire serial peripheral interface). SPI allows individually control of the device settings.

The device operates in a 3.3-V environment and is characterized for operation from –55°C to 125°C (T_case).

6 Pin Configuration and Functions

HFG Package

52-Pin CFP

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
VCC	19, 22, 23, 26, 28, 31, 32, 35, 36, 39, 41, 44, 46, 47, 48	Power	3.3-V supply. V_CC and AV_CC should always have same supply voltage. It is recommended that AV_CC use its own supply filter.
GND	Thermal pad, and Pins: 1, 7, 11, 13, 45, 51	Ground	Ground
AVCC	3, 6, 9 16, 17	Analog Power	3.3-V analog power supply. There is no internal connection between AV_CC and V_CC. It is recommended that AV_CCuse its own supply filter.
VCC_CP	10	Power	This is the charge pump power supply pin used to have the same supply as the external VCO. It can be set from 2.3 V to 3.6 V.
CTRL_LE	5	I	LVCMOS input, control latch enable for serial programmable Interface (SPI), with hysteresis. Unused or floating inputs must be tied to proper logic level. It is recommended to use a 20-kΩ or larger pullup resistor to VCC.
CTRL_CLK	4	I	LVCMOS input, serial control clock input for SPI, with hysteresis. Unused or floating inputs must be tied to proper logic level. It is recommended to use a 20-kΩ or larger pullup resistor to VCC.
CTRL_DATA	2	I	LVCMOS input, serial control data input for SPI, with hysteresis. Unused or floating inputs must be tied to proper logic level. It is recommended to use a 20-kΩ or larger pullup resistor to VCC.
PD	27	I	LVCMOS input, asynchronous power down (PD) signal. This pin is low active and can be activated external or by the corresponding bit in the SPI register (in case of logic high, the SPI setting is valid). Switches the device into power-down mode. Resets M- and N-Divider, 3-states charge pump, STATUS_REF, or PRI_SEC_CLK pin, STATUS_VCXO or I_REF_CP pin, PLL_LOCK pin, VBB pin and all Yx outputs. Sets the SPI register to default value; has internal 150-kΩ pullup resistor. It is recommended to ramp up the PD with the same time as V_CC and AV_CC or later. The ramp up rate of the PD should not be faster than the ramp up rate of V_CC and AV_CC.
RESET or HOLD	40	I	This LVCMOS input can be programmed (SPI) to act as HOLD or RESET. RESET is the default function. This pin is low active and can be activated external or via the corresponding bit in the SPI register. In case of RESET, the charge pump (CP) is switched to 3-state and all counters (N, M, P) are reset to zero (the initial divider settings are maintained in SPI registers). The LVPECL outputs are static low and high respectively and the LVCMOS outputs are all low or high if inverted. RESET is not edge triggered and should have a pulse duration of at least 5 ns.
			In case of HOLD, the CP is switched in to 3-state mode only. After HOLD is released and with the next valid reference clock cycle the charge pump is switched back in to normal operation (CP stays in 3-state as long as no reference clock is valid). During HOLD, the P divider and all outputs Yx are at normal operation. This mode allows an external control of the frequency hold-over mode.
			The input has an internal 150-kΩ pullup resistor.
VCXO_IN	21	I	VCXO LVPECL input
VCXO_IN	20	I	Complementary VCXO LVPECL input
PRI_REF	14	I	LVCMOS input for the primary reference clock, with an internal 150-kΩ pullup resistor and input hysteresis.
SEC_REF	15	I	LVCMOS input for the secondary reference clock, with an internal 150-kΩ pullup resistor and input hysteresis.
REF_SEL	12	I	LVCMOS reference clock selection input. In the manual mode the REF_SEL signal selects one of the two input clocks: REF_SEL [1]: PRI_REF is selected; REF_SEL [0]: SEC_REF is selected; The input has an internal 150-kΩ pullup resistor.
CP_OUT	8	O	Charge pump output
VBB	18	O	Bias voltage output to be used to bias unused complementary input VCXO_IN for single ended signals. The output of VBB is V_CC – 1.3 V. The output current is limited to about 1.5 mA.
STATUS_REF or PRI_SEC_CLK	50	O	This output can be programmed (SPI) to provide either the STATUS_REF or PRI_SEC_CLK information. This pin is set high if one of the STATUS conditions is valid. STATUS_REF is the default setting.
			In case of STATUS_REF, the LVCMOS output provides the Status of the Reference Clock. If a reference clock with a frequency above 2 MHz is provided to PRI_REF or SEC_REF STATUS_REF will be set high.
			In case of PRI_SEC_CLK, the LVCMOS output indicates whether the primary clock [high] or the secondary clock [low] is selected.
STATUS_VCXO or I_REF_CP	49	O	This LVCMOS output can be programmed (SPI) to provide either the STATUS_VCXO information or serve as current path for the charge pump (CP). STATUS_VCXO is the default setting.
			In case of STATUS_VCXO, the LVCMOS output provides the status of the VCXO input (frequencies above 2 MHz are interpreted as valid clock; active high).
			In case of I_REF_CP, it provides the current path for the external reference resistor (12 kΩ ±1%) to support an accurate charge pump current, optional. Do not use any capacitor across this resistor to prevent noise coupling via this node. If the internal 12 kΩ is selected (default setting), this pin can be left open.
PLL_LOCK	52	I/O	LVCMOS output for PLL_LOCK information. This pin is set high if the PLL is in lock (see feature description). This output can be programmed to be digital lock detect or analog lock detect (see feature description).
			The PLL is locked (set high), if the rising edge either of PRI_REF or SEC_REF clock and VCXO_IN clock at the phase frequency detector (PFD) are inside the lock detect window for a predetermined number of successive clock cycles.
			The PLL is out-of-lock (set low), if the rising edge of either the PRI_REF or SEC_REF) clock and VCXO_IN clock at the PFD are outside the lock detect window or if a certain frequency offset between reference frequency and feedback frequency (VCXO) is detected.
			Both, the lock detect window and the number of successive clock cycles are user definable (via SPI).
Y0A:Y0B Y1A:Y1B Y2A:Y2B Y3A:Y3B Y4A:Y4B	24, 25, 29, 30, 33, 34, 37,38, 42, 43	O	The outputs of the CDCM7005-SP are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The outputs are selectable via SPI (Word 1, Bit 2-6). The power-up setting is all outputs are LVPECL.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
V_CC, A_VCC, V_{CC_CP}	Supply voltage ⁽²⁾	–0.5	4.6	V
V_I	Input voltage ⁽³⁾	–0.5 V	V_CC + 0.5 V	V
V_O	Output voltage ⁽³⁾	–0.5	V_CC + 0.5 V	V
I_OUT	Output current for LVPECL/LVCMOS outputs (0 < V_O < V_CC)	±50		mA
I_IN	Input current (V_I < 0, V_I > V_CC)	±20		mA
T_J	Maximum junction temperature		150	°C
T_stg	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All supply voltages have to be supplied at the same time.

(3) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2500	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

		MIN	NOM	MAX	UNIT
V_CC, AV_CC	Supply voltage	3	3.3	3.6	V
V_{CC_CP}	Supply voltage	2.3		V_CC	V
V_IL	Low-level input voltage LVCMOS, see ⁽²⁾			0.3 V_CC	V
V_IH	High-level input voltage LVCMOS, see ⁽²⁾	0.7 V_CC			V
I_OH	High-level output current LVCMOS (includes all status pins)			–8	mA
I_OL	Low-level output current LVCMOS (includes all status pins)			8	mA
V_I	Input voltage range LVCMOS	0		3.6	V
V_INPP	Input amplitude LVPECL (V_{VCXO_IN} – V _{VCXO_IN} )⁽¹⁾	0.5		1.3	V
V_IC	Common-mode input voltage LVPECL	1		V_CC–0.3	V
T_C	Operating case temperature	–55		125	°C

(1) V_INPP minimum and maximum is required to maintain ac specifications; the actual device function tolerates at a minimum V_INPP
of 150 mV.

(2) V_IL and V_IH are required to maintain ac specifications; the actual device function tolerates a smaller input level of 1V, if an ac-coupling to V_CC/2 is provided.

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		CDCM7005-SP⁽²⁾	UNIT
		HFG (CFP)
		52 PINS
R_θJA	Junction-to-free-air thermal resistance⁽³⁾	21.813	°C/W
R_θJC	Junction-to-case thermal resistance⁽⁴⁾	0.849	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

(2) Connected to GND with nine thermal vias (0.3 mm diameter).

(3) Board mounted, per JESD 51-5 methodology

(4) MIL-STD-883 test method 1012

7.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP⁽¹⁾	MAX	UNIT
OVERALL
I_{CC_LVPECL}	Supply current (I_CC over frequency see Figure 2 through Figure 5)	ƒ_VCXO = 200 MHz, ƒ_{REF_IN} = 25 MHz, PFD = 195.3125 kHz, I_CP = 2 mA, all outputs are LVPECL and Div-by-8 (load, see Figure 14)		210	260	mA
I_{CC_LVCMOS}		ƒ_VCXO = 200 MHz, ƒ_{REF_IN} = 25 MHz, PFD = 195.3125 kHz, I_CP = 2 mA, All outputs are LVCMOS and Div-by-8 (load, 10 pF)		120	160	mA
I_CCPD	Power-down current	ƒ_IN = 0 MHz, V_CC = 3.6 V, AV_CC = 3.6 V, V_{CC_CP} = 3.6 V, V_I = 0 V or V_CC		100	300	µA
I_OZ	High-impedance state output current for Yx outputs	V_O = 0 V or V_CC – 0.8 V			±40	µA
I_OZ	High-impedance state output current for Yx outputs	V_O = 0 V or V_CC			±100	µA
V_{I_REF_CP}	Voltage on I_REF_CP (external current path for accurate charge pump current)	12 kΩ to GND at pin 49	1.114	1.21	1.326	V
V_BB	Output reference voltage	V_CC = 3 V – 3.6 V; I_BB = –0.2 mA	V_CC–1.446	V_CC–1.3	V_CC–1.09	V
C_O	Output capacitance for Yx	V_CC = 3.3 V, V_O = 0 V or V_CC		3		pF
C_I	Input capacitance at PRI_REF and SEC_REF	V_I = 0 V or V_CC, V_I = 0 V or V_CC		3.6		pF
C_I	Input capacitance at CTRL_LE, CTRL_CLOCK, CTRL_DATA	V_I = 0 V or V_CC		3		pF
LVCMOS
ƒ_clk	Output frequency (see ⁽²⁾, ⁽³⁾, Figure 7, and Figure 8)	Load = 5 pF to GND, 1 kΩ to V_CC, 1 kΩ to GND		240		MHz
V_IK	LVCMOS input clamp voltage	V_CC = 3 V, I_I = –18 mA			–1.2	V
I_I	LVCMOS input current for CTRL_LE, CTRL_CLK, CTRL_DATA	V_I = 0 V or V_CC, V_CC = 3.6 V			±5	µA
I_IH	LVCMOS input current for PD, RESET, HOLD, REF_SEL, PRI_REF, SEC_REF, (see ⁽⁴⁾)	V_I = V_CC, V_CC = 3.6 V			5	µA
I_IL	LVCMOS input current for PD, RESET, HOLD, REF_SEL, PRI_REF, SEC_REF (see ⁽⁴⁾)	V_I = 0 V, V_CC = 3.6 V	–15		–35	µA
V_OH	High-level output voltage for LVCMOS outputs	V_CC = min to max, I_OH = –100 μA	V_CC–0.1			V
		V_CC = 3 V, I_OH = –6 mA	2.4
		V_CC = 3 V, I_OH = –12 mA	2
V_OL	Low-level output voltage for LVCMOS outputs	V_CC = min to max, I_OL = 100 μA			0.1	V
		V_CC = 3 V, I_OL = 6 mA			0.5
		V_CC = 3 V, I_OL = 12 mA			0.8
I_OH	High-level output current	V_CC = 3.3 V, V_O = 1.65 V	–50	–30	–20	mA
I_OL	Low-level output current	V_CC = 3.3 V, V_O = 1.65 V	20	30	50	mA
tpho	Phase offset (REF_IN to Y output)⁽⁶⁾	VREF_IN = V_CC/2, Y = V_CC/2, see Figure 12, Load = 10 pF		2.7		ns
t_sk(p)	LVCMOS pulse skew, see Figure 11	Crosspoint to V_CC/2 load, see Figure 13		160		ps
t_pd(LH)	Propagation delay from VCXO_IN to Yx, see Figure 11	Crosspoint to V_CC/2, Load = 10 pF, see Figure 13 (PLL bypass mode)		2.8		ns
t_pd(HL)	Propagation delay from VCXO_IN to Yx, see Figure 11			2.8		ns
t_sk(o)	LVCMOS single-ended output skew, see ⁽⁷⁾ and Figure 11	All outputs have the same divider ratio		80		ps
t_sk(o)	LVCMOS single-ended output skew, see ⁽⁷⁾ and Figure 11	Outputs have different divider ratios		80		ps
Duty cycle	LVCMOS	V_CC/2 to V_CC/2	49%		51%
t_slew-rate	Output rise/fall slew rate	20% to 80% of swing (load see Figure 13)		3.5		V/ns
LVPECL
ƒ_clk	Output frequency, see ⁽³⁾ and Figure 6	Load, see Figure 14	0	2000		MHz
I_I	LVPECL input current	V_I = 0 V or V_CC			±20	µA
V_OH	LVPECL high-level output voltage	Load, See Figure 14	V_CC–1.18		V_CC–0.81	V
V_OL	LVPECL low-level output voltage	Load, See Figure 14	V_CC–2		V_CC–1.55	V
\|V_OD\|	Differential output voltage	See Figure 10 and load, see Figure 14	500			mV
t_pho	Phase offset (REF_IN to Y output)⁽⁷⁾	VREF_IN = V_CC/2 to cross point of Y, see Figure 12		250		ps
t_pd(LH)	Propagation delay time, VCXO_IN to Yx, see Figure 11	Cross point-to-cross point, load see Figure 14		615		ps
t_pd(HL)	Propagation delay time, VCXO_IN to Yx, see Figure 11	Cross point-to-cross point, load see Figure 14		615		ps
t_sk(p)	LVPECL pulse skew, see Figure 11	Cross point-to-cross point, load see Figure 14		15		ps
t_sk(o)	LVPECL output skew⁽⁷⁾	Load see Figure 14, all outputs have the same divider ratio		20		ps
t_sk(o)	LVPECL output skew⁽⁷⁾	Load see Figure 14, outputs have different divider ratios		50		ps
t_r / t_f	Rise and fall time	20% to 80% of V_OUTPP, see Figure 10		170		ps
C_I	Input capacitance at VCXO_IN, VCXO_IN			2.5		pF
LVCMOS-TO-LVPECL
t_{sk(P_C)}	Output skew between LVCMOS and LVPECL outputs, see ⁽⁸⁾ and Figure 11	Cross point to V_CC/2; load, see Figure 13 and Figure 14		2	3.2	ns
PLL ANALOG LOCK
I_OH	High-level output current	V_CC = 3.6 V, V_O = 1.8 V	–150	–110	–80	µA
I_OL	Low-level output current	V_CC = 3.6 V, V_O = 1.8 V	80	110	150	µA
I_{OZH LOCK}	High-impedance state output current for PLL LOCK output⁽⁵⁾	V_O = 3.6 V (PD is set low)		45	65	µA
I_{OZL LOCK}	High-impedance state output current for PLL LOCK output⁽⁵⁾	V_O = 0 V (PD is set low)			±5	µA
V_IT+	Positive input threshold voltage	V_CC = min to max		V_CC×0.55		V
V_IT–	Negative input threshold voltage	V_CC = min to max		V_CC×0.35		V
PHASE DETECTOR
ƒ_CPmax	Maximum charge pump frequency	Default PFD pulse width delay		100		MHz
CHARGE PUMP
I_CP	Charge pump sink/source current range ⁽⁹⁾	V_CP = 0.5 V_{CC_CP}	±0.2		±3.9	mA
I_CP3St	Charge pump 3-state current	Temperature = 25°C, 0.5 V < V_CP < V_{CC_CP} – 0.5 V	–10		10	nA
I_CP3St	Charge pump 3-state current	Temperature = –55°C to 125°C, 0.5 V < V_CP < V_{CC_CP} – 0.5 V	–50		50	nA
I_CPA	ICP absolute accuracy	V_CP = 0.5 V_{CC_CP}, internal reference resistor, SPI default settings	–20%	10%	20%
I_CPA	ICP absolute accuracy	V_CP = 0.5 V_{CC_CP}, external reference resistor 12 kΩ (1%) at I_REF_CP, SPI default settings		5%
I_CPM	Sink/source current matching	0.5 V < V_CP < V_{CC_CP} – 0.5 V, SPI default settings	–7%	2.5%	7%
I_VCPM	ICP vs VCP matching	0.5 V < V_CP < V_{CC_CP} – 0.5 V	–10%	5%	10%

(1) All typical values are at V_CC = 3.3 V, temperature = 25°C.

(2) ƒ_clk can be up to 400 MHz in the typical operating mode (25°C / 3.3-V V_CC).

(3) Operating the LVCMOS or LVPECL output above the maximum frequency will not cause a malfunction to the device, but the output signal swing may no longer meet the output specification.

(4) These inputs have an internal 150-kΩ pullup resistor.

(5) Lock output has an 80-kΩ pulldown resistor.

(6) This is valid only for the same frequency of REF_IN clock and Y output clock. It can be adjusted by the SPI controller (reference delay M and VCXO delay N).

(7) The t_sk(o) specification is only valid for equal loading of all outputs.

(8) The phase of LVCMOS is lagging in reference to the phase of LVPECL.

(9) Defined by SPI settings.

7.6 Timing Requirements

over recommended ranges of supply voltage, load and operating free air temperature

		MIN	TYP	MAX	UNIT
PRI_REF/SEC_REF_IN REQUIREMENTS
ƒ_{REF_IN}	LVCMOS primary or secondary reference clock frequency⁽¹⁾ ⁽⁴⁾	0		200	MHz
t_r/ t_f	Rise and fall time of PRI_REF or SEC_REF signals from 20% to 80% of V_CC			4	ns
dutyREF	Duty cycle of PRI_REF or SEC_REF at V_CC/2	40%		60%
VCXO_IN, VCXO_IN REQUIREMENTS
ƒ_{VCXO_IN}	VCXO clock frequency⁽²⁾	0	2000		MHz
t_r/ t_f	Rise and fall time 20% to 80% of VINPP at 80 MHz to 800 MHz⁽³⁾			3	ns
dutyVCXO	Duty cycle of VCXO clock	40%		60%
SPI/CONTROL REQUIREMENTS (see Figure 24)
ƒ_{CTRL_CLK}	CTRL_CLK frequency			20	MHz
t_su1	CTRL_DATA to CTRL_CLK setup time	10			ns
t_h2	CTRL_DATA to CTRL_CLK hold time	10			ns
t₃	CTRL_CLK high duration	25			ns
t₄	CTRL_CLK low duration	25			ns
t_su5	CTRL_LE to CTRL_CLK setup time	10			ns
t_su6	CTRL_CLK to CTRL_LE setup time	10			ns
t₇	CTRL_LE pulse width	20			ns
t_r/ t_f	Rise and fall time of CTRL_DATA CTRL_CLK, CTRL_LE from 20% to 80% of V_CC			4	ns
PD, RESET, HOLD , REF_SEL REQUIREMENTS
t_r / t_f	Rise and fall time of the PD, RESET, HOLD, REF_SEL signal from 20% to 80% of V_CC			4	ns

(1) At Reference Clock less than 2 MHz, the device stays in normal operation mode but the frequency detection circuitry resets the STATUS_REF signal to low. In this case, the status of the STATUS_REF is no longer relevant.

(2) If the Feedback Clock (derives from VCXO input) is less than 2 MHz, the device stays in normal operation mode but the frequency detection circuitry resets the STATUS_VCXO signal and PLL_LOCK signal to low. Both status signals are no longer relevant. This effects the HOLD-over function as well, as the PLL_LOCK signal is no longer valid!

(3) Use a square wave for lower frequencies (<80 MHz).

(4) ƒ_{REF_IN} can be up to 250 MHz in typical operating mode (25°C / 3.3-V V_CC).

Figure 1. CDCM7005-SPHFG-V - 52-Pin HFG Package
Operating Life Derating Chart

7.7 Typical Characteristics

If div-by-2/4/8/16 is activated for one or more outputs, 'Δ for div-by-2/4/8/16' has to be added to I_CC of div-by-1. If div-by-3 or div-by-6 is activated, 'Δ for div-by-2/4/8/16' and 'Δ for div-by-3/6' has to be added to I_CC of div-by-1.

Figure 2. LVPECL Supply Current vs Number of Active Outputs

To estimate I_CC with different P-divider settings use 'Δ for div-by-2/4/8/16' and 'Δ for div-by-3/6' of Figure 2

Figure 4. LVCMOS Supply Current / Device Power Consumption vs Number Of Active Outputs (Load = 5 pF)

Figure 6. Differential LVPECL Output Voltage vs Output Frequency

Figure 8. LVCMOS Output Swing vs Frequency

Figure 3. LVPECL Device Power Consumption vs Number of Active Outputs

To estimate I_CC with different P-divider settings use 'Δ for div-by-2/4/8/16' and 'Δ for div-by-3/6' of Figure 2

Figure 5. LVCMOS Supply Current / Device Power Consumption vs Number of Active Outputs (Load = 10 pF)

Figure 7. LVCMOS Output Swing vs Frequency

Figure 9. Output Reference Voltage (VBB) vs Load