SLOS739A July   2012  – March 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics - I/O Pin Characteristics
    6. 7.6  Master Clock Characteristics
    7. 7.7  Speaker Amplifier Characteristics
    8. 7.8  Headphone Amplifier and Line Driver Characteristics
    9. 7.9  Protection Characteristics
    10. 7.10 I2C Serial Control Port Requirements and Specifications
    11. 7.11 Serial Audio Port Timing
    12. 7.12 Typical Characteristics
      1. 7.12.1 Headphone Typical Characteristics
      2. 7.12.2 Line Driver Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power Supply
      2. 9.3.2  I2C Address Selection and Fault Output
      3. 9.3.3  Device Protection System
        1. 9.3.3.1 Overcurrent (OC) Protection With Current Limiting
        2. 9.3.3.2 Overtemperature Protection
        3. 9.3.3.3 Undervoltage Protection (UVP) and Power-On Reset (POR)
      4. 9.3.4  Clock, Auto Detection, and PLL
      5. 9.3.5  PWM Section
      6. 9.3.6  SSTIMER Functionality
      7. 9.3.7  2.1-Mode Support
        1. 9.3.7.1 Supply Pumping and Polarity Inversion for 2.1 Mode
      8. 9.3.8  PBTL-Mode Support
      9. 9.3.9  I2C Serial Control Interface
        1. 9.3.9.1 Single- and Multiple-Byte Transfers
        2. 9.3.9.2 Single-Byte Write
        3. 9.3.9.3 Multiple-Byte Write
        4. 9.3.9.4 Single-Byte Read
        5. 9.3.9.5 Multiple-Byte Read
      10. 9.3.10 Dynamic Range Control (DRC)
      11. 9.3.11 Bank Switching
      12. 9.3.12 Serial Data Interface
        1. 9.3.12.1 Serial Interface Control and Timing
          1. 9.3.12.1.1 I2S Timing
          2. 9.3.12.1.2 Left-Justified
          3. 9.3.12.1.3 Right-Justified
      13. 9.3.13 DirectPath Headphone/Line Driver
        1. 9.3.13.1 Using Headphone Amplifier in TAS5721
        2. 9.3.13.2 Using Line Driver Amplifier in TAS5721
    4. 9.4 Device Functional Modes
      1. 9.4.1 Output Mode and MUX Selection
    5. 9.5 Programming
      1. 9.5.1 General I2C Operation
        1. 9.5.1.1 I2C Device Address Change Procedure
      2. 9.5.2 26-Bit 3.23 Number Format
    6. 9.6 Register Maps
      1. 9.6.1  Clock Control Register (0x00)
      2. 9.6.2  Device ID Register (0x01)
      3. 9.6.3  Error Status Register (0x02)
      4. 9.6.4  System Control Register 1 (0x03)
      5. 9.6.5  Serial Data Interface Register (0x04)
      6. 9.6.6  System Control Register 2 (0x05)
      7. 9.6.7  Soft Mute Register (0x06)
      8. 9.6.8  Volume Registers (0x07, 0x08, 0x09, 0x0A)
      9. 9.6.9  Volume Configuration Register (0x0E)
      10. 9.6.10 Modulation Limit Register (0x10)
      11. 9.6.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)
      12. 9.6.12 Pwm Shutdown Group Register (0x19)
      13. 9.6.13 Start/stop Period Register (0x1A)
      14. 9.6.14 Oscillator Trim Register (0x1B)
      15. 9.6.15 BKND_ERR Register (0x1C)
      16. 9.6.16 Input Multiplexer Register (0x20)
      17. 9.6.17 Channel 4 Source Select Register (0x21)
      18. 9.6.18 PWM Output MUX Register (0x25)
      19. 9.6.19 DRC Control (0x46)
      20. 9.6.20 Bank Switch and EQ Control (0x50)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Component Selection and Hardware Connections
        2. 10.2.2.2 I2C Pullup Resistors
        3. 10.2.2.3 Digital I/O Connectivity
        4. 10.2.2.4 Recommended Startup and Shutdown Procedures
          1. 10.2.2.4.1 Recommended Use Model
            1. 10.2.2.4.1.1 Initialization Sequence
            2. 10.2.2.4.1.2 Normal Operation
            3. 10.2.2.4.1.3 Shutdown Sequence
            4. 10.2.2.4.1.4 Power-Down Sequence
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
    1. 11.1 DVDD and AVDD Supplies
    2. 11.2 PVDD Power Supply
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

1 Features

  • Audio Input/Output
    • 10 W x 2 into 8 Ω With PVDD = 24 V
    • 8 W x 2 + 12 W x 1 into 8 Ω With PVDD = 24 V
    • Supports 2.0, Single Device 2.1, and Mono Modes
    • Supports 8-kHz to 48-kHz Sample Rate (LJ/RJ/I2S)
    • Integrated DirectPath™ Headphone Amplifier and 2 VRMS Line Driver
  • Audio/PWM Processing
    • Independent Channel Volume Controls With 24-dB to Mute in 0.5 dB Steps
    • Separate Dynamic Range Control for Satellite and Sub Channels
    • 21 Programmable Biquads for Speaker EQ
    • Programmable Two-Band Dynamic Range Control
    • Support for 3D Effects
  • General Features
    • I2C™ Serial Control Interface Operational Without MCLK
    • Configurable I2C Address (0x34 or 0x36)
    • Automatic Sample Rate Detection
    • Thermal and Short-Circuit Protection
    • Wide PVDD Supply Range (4.5 V to 24 V)

2 Applications

    LED/LCD TVs, Soundbar, Docking Stations, PC Speakers

3 Description

The TAS5721 is an efficient, digital-input audio amplifier for driving 2.0 speaker systems configured as a bridge tied load (BTL), 2.1 systems with two satellite speakers and one subwoofer, or in PBTL systems driving a single speaker configured as a parallel bridge tied load (PBTL). One serial data input allows processing of up to two discrete audio channels and seamless integration to most digital audio processors and MPEG decoders. The device accepts a wide range of input data formats and sample rates. A fully programmable data path routes these channels to the internal speaker drivers.

The TAS5721 is a slave-only device, receiving all clocks from external sources. The TAS5721 operates with a PWM carrier frequency between a 384-kHz switching rate and a 288-KHz switching rate, depending on the input sample rate. Oversampling, combined with a fourth-order noise shaper, provides a flat noise floor and excellent dynamic range from 20 Hz to 20 kHz.

An integrated ground centered DirectPath™ combination headphone amplifier and 2VRMS line driver is integrated in the TAS5721.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TAS5721 HTSSOP (48) 12.50 mm × 6.10 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Output Power vs. PVDD in 2.0 Mode

TAS5721 C001_PVDDvPo8Vto24V4R6R8R.png

Signal Processing Flow

TAS5721 signal_processing_flow_slos739.gif
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