ZHCSIG6A
July 2018 – October 2018
DS90UH940N-Q1
PRODUCTION DATA.
1
特性
2
应用
3
说明
Device Images
典型应用
4
修订历史记录
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
DC Electrical Characteristics
6.6
AC Electrical Characteristics
6.7
Timing Requirements for the Serial Control Bus
6.8
Switching Characteristics
6.9
Timing Diagrams and Test Circuits
6.10
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
High-Speed Forward Channel Data Transfer
7.3.2
Low-Speed Back Channel Data Transfer
7.3.3
FPD-Link III Port Register Access
7.3.4
Clock and Output Status
7.3.5
LVCMOS VDDIO Option
7.3.6
Power Down (PDB)
7.3.7
Interrupt Pin — Functional Description and Usage (INTB_IN)
7.3.8
General-Purpose I/O (GPIO)
7.3.8.1
GPIOx and D_GPIOx Pin Configuration
7.3.8.2
Back Channel Configuration
7.3.8.3
GPIO_REG[8:5] Configuration
7.3.9
SPI Communication
7.3.9.1
SPI Mode Configuration
7.3.9.2
Forward Channel SPI Operation
7.3.9.3
Reverse Channel SPI Operation
7.3.10
Backward Compatibility
7.3.11
Adaptive Equalizer
7.3.11.1
Transmission Distance
7.3.11.2
Adaptive Equalizer Algorithm
7.3.11.3
AEQ Settings
7.3.11.3.1
AEQ Start-Up and Initialization
7.3.11.3.2
AEQ Range
7.3.11.3.3
AEQ Timing
7.3.12
I2S Audio Interface
7.3.12.1
I2S Transport Modes
7.3.12.2
I2S Jitter Cleaning
7.3.12.3
MCLK
7.3.13
HDCP
7.3.13.1
HDCP I2S Audio Encryption
7.3.14
Built-In Self Test (BIST)
7.3.14.1
BIST Configuration And Status
7.3.14.1.1
Sample BIST Sequence
7.3.14.2
Forward Channel and Back Channel Error Checking
7.3.15
Internal Pattern Generation
7.4
Device Functional Modes
7.4.1
Configuration Select
7.4.1.1
1-Lane FPD-Link III Input, 4 MIPI® Lanes Output
7.4.1.2
1-Lane FPD-Link III Input, 2 MIPI® Lanes Output
7.4.1.3
2-Lane FPD-Link III Input, 4 MIPI® Lanes Output
7.4.1.4
2-Lane FPD-Link III Input, 2 MIPI® Lanes Output
7.4.1.5
1- or 2-Lane FPD-Link III Input, 2 or 4 MIPI® Lanes Output in Replicate
7.4.2
MODE_SEL[1:0]
7.4.3
CSI-2 Interface
7.4.4
Input Display Timing
7.4.5
MIPI® CSI-2 Output Data Formats
7.4.6
Non-Continuous / Continuous Clock
7.4.7
Ultra-Low-Power State (ULPS)
7.4.8
CSI-2 Data Identifier
7.5
Programming
7.5.1
Serial Control Bus
7.5.2
Multi-Master Arbitration Support
7.5.3
I2C Restrictions on Multi-Master Operation
7.5.4
Multi-Master Access to Device Registers for Newer FPD-Link III Devices
7.5.5
Multi-Master Access to Device Registers for Older FPD-Link III Devices
7.5.6
Restrictions on Control Channel Direction for Multi-Master Operation
7.6
Register Maps
7.6.1
DS90UH940N-Q1 Registers
7.6.1.1
I2C_Device_ID Register (Address = 0h) [reset = Strap]
Table 12.
I2C_Device_ID Register Field Descriptions
7.6.1.2
Reset Register (Address = 1h) [reset = 4h]
Table 13.
Reset Register Field Descriptions
7.6.1.3
General_Configuration_0 Register (Address = 2h) [reset = 0h]
Table 14.
General_Configuration_0 Register Field Descriptions
7.6.1.4
General_Configuration_1 Register (Address = 3h) [reset = F0h]
Table 15.
General_Configuration_1 Register Field Descriptions
7.6.1.5
BCC_Watchdog_Control Register (Address = 4h) [reset = FEh]
Table 16.
BCC_Watchdog_Control Register Field Descriptions
7.6.1.6
I2C_Control_1 Register (Address = 5h) [reset = 1Eh]
Table 17.
I2C_Control_1 Register Field Descriptions
7.6.1.7
I2C_Control_2 Register (Address = 6h) [reset = 0h]
Table 18.
I2C_Control_2 Register Field Descriptions
7.6.1.8
REMOTE_ID Register (Address = 7h) [reset = 0h]
Table 19.
REMOTE_ID Register Field Descriptions
7.6.1.9
SlaveID_0 Register (Address = 8h) [reset = 0h]
Table 20.
SlaveID_0 Register Field Descriptions
7.6.1.10
SlaveID_1 Register (Address = 9h) [reset = 0h]
Table 21.
SlaveID_1 Register Field Descriptions
7.6.1.11
SlaveID_2 Register (Address = Ah) [reset = 0h]
Table 22.
SlaveID_2 Register Field Descriptions
7.6.1.12
SlaveID_3 Register (Address = Bh) [reset = 0h]
Table 23.
SlaveID_3 Register Field Descriptions
7.6.1.13
SlaveID_4 Register (Address = Ch) [reset = 0h]
Table 24.
SlaveID_4 Register Field Descriptions
7.6.1.14
SlaveID_5 Register (Address = Dh) [reset = 0h]
Table 25.
SlaveID_5 Register Field Descriptions
7.6.1.15
SlaveID_6 Register (Address = Eh) [reset = 0h]
Table 26.
SlaveID_6 Register Field Descriptions
7.6.1.16
SlaveID_7 Register (Address = Fh) [reset = 0h]
Table 27.
SlaveID_7 Register Field Descriptions
7.6.1.17
SlaveAlias_0 Register (Address = 10h) [reset = 0h]
Table 28.
SlaveAlias_0 Register Field Descriptions
7.6.1.18
SlaveAlias_1 Register (Address = 11h) [reset = 0h]
Table 29.
SlaveAlias_1 Register Field Descriptions
7.6.1.19
SlaveAlias_2 Register (Address = 12h) [reset = 0h]
Table 30.
SlaveAlias_2 Register Field Descriptions
7.6.1.20
SlaveAlias_3 Register (Address = 13h) [reset = 0h]
Table 31.
SlaveAlias_3 Register Field Descriptions
7.6.1.21
SlaveAlias_4 Register (Address = 14h) [reset = 0h]
Table 32.
SlaveAlias_4 Register Field Descriptions
7.6.1.22
SlaveAlias_5 Register (Address = 15h) [reset = 0h]
Table 33.
SlaveAlias_5 Register Field Descriptions
7.6.1.23
SlaveAlias_6 Register (Address = 16h) [reset = 0h]
Table 34.
SlaveAlias_6 Register Field Descriptions
7.6.1.24
SlaveAlias_7 Register (Address = 17h) [reset = 0h]
Table 35.
SlaveAlias_7 Register Field Descriptions
7.6.1.25
MAILBOX_18 Register (Address = 18h) [reset = 0h]
Table 36.
MAILBOX_18 Register Field Descriptions
7.6.1.26
MAILBOX_19 Register (Address = 19h) [reset = 1h]
Table 37.
MAILBOX_19 Register Field Descriptions
7.6.1.27
GPIO_9__Global_GPIO_Config Register (Address = 1Ah) [reset = 0h]
Table 38.
GPIO_9__Global_GPIO_Config Register Field Descriptions
7.6.1.28
Frequency_Counter Register (Address = 1Bh) [reset = 0h]
Table 39.
Frequency_Counter Register Field Descriptions
7.6.1.29
General_Status Register (Address = 1Ch) [reset = 0h]
Table 40.
General_Status Register Field Descriptions
7.6.1.30
GPIO0_Config Register (Address = 1Dh) [reset = 0h]
Table 41.
GPIO0_Config Register Field Descriptions
7.6.1.31
GPIO1_2_Config Register (Address = 1Eh) [reset = 0h]
Table 42.
GPIO1_2_Config Register Field Descriptions
7.6.1.32
GPIO_3_Config Register (Address = 1Fh) [reset = 0h]
Table 43.
GPIO_3_Config Register Field Descriptions
7.6.1.33
GPIO_5_6_Config Register (Address = 20h) [reset = 0h]
Table 44.
GPIO_5_6_Config Register Field Descriptions
7.6.1.34
GPIO_7_8_Config Register (Address = 21h) [reset = 0h]
Table 45.
GPIO_7_8_Config Register Field Descriptions
7.6.1.35
Datapath_Control Register (Address = 22h) [reset = 0h]
Table 46.
Datapath_Control Register Field Descriptions
7.6.1.36
RX_Mode_Status Register (Address = 23h) [reset = Strap]
Table 47.
RX_Mode_Status Register Field Descriptions
7.6.1.37
BIST_Control Register (Address = 24h) [reset = 8h]
Table 48.
BIST_Control Register Field Descriptions
7.6.1.38
BIST_ERROR_COUNT Register (Address = 25h) [reset = 0h]
Table 49.
BIST_ERROR_COUNT Register Field Descriptions
7.6.1.39
SCL_High_Time Register (Address = 26h) [reset = 83h]
Table 50.
SCL_High_Time Register Field Descriptions
7.6.1.40
SCL_Low_Time Register (Address = 27h) [reset = 84h]
Table 51.
SCL_Low_Time Register Field Descriptions
7.6.1.41
Datapath_Control_2 Register (Address = 28h) [reset = Loaded from SER]
Table 52.
Datapath_Control_2 Register Field Descriptions
7.6.1.42
I2S_Control Register (Address = 2Bh) [reset = 0h]
Table 53.
I2S_Control Register Field Descriptions
7.6.1.43
PCLK_Test_Mode Register (Address = 2Eh) [reset = 0h]
Table 54.
PCLK_Test_Mode Register Field Descriptions
7.6.1.44
DUAL_RX_CTL Register (Address = 34h) [reset = 1h]
Table 55.
DUAL_RX_CTL Register Field Descriptions
7.6.1.45
AEQ_CTL1 Register (Address = 35h) [reset = 0h]
Table 56.
AEQ_CTL1 Register Field Descriptions
7.6.1.46
MODE_SEL Register (Address = 37h) [reset = 0h]
Table 57.
MODE_SEL Register Field Descriptions
7.6.1.47
I2S_DIVSEL Register (Address = 3Ah) [reset = 0h]
Table 58.
I2S_DIVSEL Register Field Descriptions
7.6.1.48
Adaptive_EQ_Status Register (Address = 3Bh) [reset = 0h]
Table 59.
Adaptive_EQ_Status Register Field Descriptions
7.6.1.49
LINK_ERROR_COUNT Register (Address = 41h) [reset = 3h]
Table 60.
LINK_ERROR_COUNT Register Field Descriptions
7.6.1.50
HSCC_CONTROL Register (Address = 43h) [reset = 0h]
Table 61.
HSCC_CONTROL Register Field Descriptions
7.6.1.51
ADAPTIVE_EQ_BYPASS Register (Address = 44h) [reset = 60h]
Table 62.
ADAPTIVE_EQ_BYPASS Register Field Descriptions
7.6.1.52
AEQ_CTL2 Register (Address = 45h) [reset = 88h]
Table 63.
AEQ_CTL2 Register Field Descriptions
7.6.1.53
CML_OUTPUT_CTL1 Register (Address = 52h) [reset = 0h]
Table 64.
CML_OUTPUT_CTL1 Register Field Descriptions
7.6.1.54
CML_OUTPUT_ENABLE Register (Address = 56h) [reset = 0h]
Table 65.
CML_OUTPUT_ENABLE Register Field Descriptions
7.6.1.55
CML_OUTPUT_CTL2 Register (Address = 57h) [reset = 0h]
Table 66.
CML_OUTPUT_CTL2 Field Descriptions
7.6.1.56
CML_OUTPUT_CTL3 Register (Address = 63h) [reset = 0h]
Table 67.
CML_OUTPUT_CTL3 Field Descriptions
7.6.1.57
PGCTL Register (Address = 64h) [reset = 10h]
Table 68.
PGCTL Register Field Descriptions
7.6.1.58
PGCFG Register (Address = 65h) [reset = 0h]
Table 69.
PGCFG Register Field Descriptions
7.6.1.59
PGIA Register (Address = 66h) [reset = 0h]
Table 70.
PGIA Register Field Descriptions
7.6.1.60
PGID Register (Address = 67h) [reset = 0h]
Table 71.
PGID Register Field Descriptions
7.6.1.61
PGDBG Register (Address = 68h) [reset = 0h]
Table 72.
PGDBG Register Field Descriptions
7.6.1.62
PGTSTDAT Register (Address = 69h) [reset = 0h]
Table 73.
PGTSTDAT Register Field Descriptions
7.6.1.63
CSICFG0 Register (Address = 6Ah) [reset = 0h]
Table 74.
CSICFG0 Register Field Descriptions
7.6.1.64
CSICFG1 Register (Address = 6Bh) [reset = 0h]
Table 75.
CSICFG1 Register Field Descriptions
7.6.1.65
CSIIA Register (Address = 6Ch) [reset = 0h]
Table 76.
CSIIA Register Field Descriptions
7.6.1.66
CSIID Register (Address = 6Dh) [reset = 0h]
Table 77.
CSIID Register Field Descriptions
7.6.1.67
GPIO_Pin_Status_1 Register (Address = 6Eh) [reset = 0h]
Table 78.
GPIO_Pin_Status_1 Register Field Descriptions
7.6.1.68
GPIO_Pin_Status_2 Register (Address = 6Fh) [reset = 0h]
Table 79.
GPIO_Pin_Status_2 Register Field Descriptions
7.6.1.69
RX_BKSV0 Register (Address = 80h) [reset = 0h]
Table 80.
RX_BKSV0 Register Field Descriptions
7.6.1.70
RX_BKSV1 Register (Address = 81h) [reset = 0h]
Table 81.
RX_BKSV1 Register Field Descriptions
7.6.1.71
RX_BKSV2 Register (Address = 82h) [reset = 0h]
Table 82.
RX_BKSV2 Register Field Descriptions
7.6.1.72
RX_BKSV3 Register (Address = 83h) [reset = 0h]
Table 83.
RX_BKSV3 Register Field Descriptions
7.6.1.73
RX_BKSV4 Register (Address = 84h) [reset = 0h]
Table 84.
RX_BKSV4 Register Field Descriptions
7.6.1.74
TX_KSV0 Register (Address = 90h) [reset = 0h]
Table 85.
TX_KSV0 Register Field Descriptions
7.6.1.75
TX_KSV1 Register (Address = 91h) [reset = 0h]
Table 86.
TX_KSV1 Register Field Descriptions
7.6.1.76
TX_KSV2 Register (Address = 92h) [reset = 0h]
Table 87.
TX_KSV2 Register Field Descriptions
7.6.1.77
TX_KSV3 Register (Address = 93h) [reset = 0h]
Table 88.
TX_KSV3 Register Field Descriptions
7.6.1.78
TX_KSV4 Register (Address = 94h) [reset = 0h]
Table 89.
TX_KSV4 Register Field Descriptions
7.6.1.79
HDCP_DBG Register (Address = C0h) [reset = 0h]
Table 90.
HDCP_DBG Register Field Descriptions
7.6.1.80
HDCP_DBG2 Register (Address = C1h) [reset = 0h]
Table 91.
HDCP_DBG2 Register Field Descriptions
7.6.1.81
HDCP_STS Register (Address = C4h) [reset = 0h]
Table 92.
HDCP_STS Register Field Descriptions
7.6.1.82
KSV_FIFO_DATA Register (Address = C9h) [reset = 0h]
Table 93.
KSV_FIFO_DATA Register Field Descriptions
7.6.1.83
KSV_FIFO_ADDR0 Register (Address = CAh) [reset = 0h]
Table 94.
KSV_FIFO_ADDR0 Register Field Descriptions
7.6.1.84
KSV_FIFO_ADDR1 Register (Address = CBh) [reset = 0h]
Table 95.
KSV_FIFO_ADDR1 Register Field Descriptions
7.6.1.85
RPTR_TX0 Register (Address = E0h) [reset = 0h]
Table 96.
RPTR_TX0 Register Field Descriptions
7.6.1.86
RPTR_TX1 Register (Address = E1h) [reset = 0h]
Table 97.
RPTR_TX1 Register Field Descriptions
7.6.1.87
RPTR_TX2 Register (Address = E2h) [reset = 0h]
Table 98.
RPTR_TX2 Register Field Descriptions
7.6.1.88
RPTR_TX3 Register (Address = E3h) [reset = 0h]
Table 99.
RPTR_TX3 Register Field Descriptions
7.6.1.89
HDCP_RX_ID0 Register (Address = F0h) [reset = 5Fh]
Table 100.
HDCP_RX_ID0 Register Field Descriptions
7.6.1.90
HDCP_RX_ID1 Register (Address = F1h) [reset = 55h]
Table 101.
HDCP_RX_ID1 Register Field Descriptions
7.6.1.91
HDCP_RX_ID2 Register (Address = F2h) [reset = 48h]
Table 102.
HDCP_RX_ID2 Register Field Descriptions
7.6.1.92
HDCP_RX_ID3 Register (Address = F3h) [reset = 39h]
Table 103.
HDCP_RX_ID3 Register Field Descriptions
7.6.1.93
HDCP_RX_ID4 Register (Address = F4h) [reset = 34h]
Table 104.
HDCP_RX_ID4 Register Field Descriptions
7.6.1.94
HDCP_RX_ID5 Register (Address = F5h) [reset = 30h]
Table 105.
HDCP_RX_ID5 Register Field Descriptions
7.6.2
CSI-2 Indirect Registers
7.6.2.1
CSI_TCK_TRAIL Register (Address = 2h) [reset = 0h]
Table 107.
CSI_TCK_TRAIL Register Field Descriptions
7.6.2.2
RAW_ALIGN Register (Address = 9h) [reset = 0h]
Table 108.
RAW_ALIGN Register Field Descriptions
7.6.2.3
CSI_EN_PORT0 Register (Address = 13h) [reset = 3Fh]
Table 109.
CSI_EN_PORT0 Register Field Descriptions
7.6.2.4
CSI_EN_PORT1 Register (Address = 14h) [reset = 0h]
Table 110.
CSI_EN_PORT1 Register Field Descriptions
7.6.2.5
CSIPASS Register (Address = 16h) [reset = 2h]
Table 111.
CSIPASS Register Field Descriptions
7.6.2.6
CSI_VC_ID Register (Address = 2Eh) [reset = 0h]
Table 112.
CSI_VC_ID Register Field Descriptions
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
FPD-Link III Interconnect Guidelines
8.2.3
Application Curves
9
Power Supply Recommendations
9.1
Power-Up Requirements and PDB Pin
9.2
Power Sequence
10
Layout
10.1
Layout Guidelines
10.2
Ground
10.3
Routing FPD-Link III Signal Traces
10.4
CSI-2 Guidelines
10.5
Layout Example
11
器件和文档支持
11.1
文档支持
11.1.1
相关文档
11.2
接收文档更新通知
11.3
社区资源
11.4
商标
11.5
静电放电警告
11.6
术语表
12
机械、封装和可订购信息
1
特性
具有符合 AEC Q100 标准的下列结果：
器件温度等级 2：–40°C 至 +105°C 环境工作温度范围
支持高达 170MHz 的像素时钟频率，可实现 WUXGA (1920×1200) 和 1080p60 分辨率和 24 位色深
具有偏移补偿能力的单通道或双通道 FPD-Link III 接口
MIPI®D-PHY/CSI-2 发送器
具有可选的 2 通道或 4 通道操作（每个通道最高 1.3Gbps）的 CSI-2 输出端口
视频格式：RGB888/666/565，YUV422/420，RAW8/10/12
可编程虚拟通道标识符
具有片上密钥存储的集成型 HDCP 密码引擎
四通道高速 GPIO（每个通道最高 2Mbps）
自适应接收均衡
1.7GHz 时，通道插入损耗补偿高达 –15.3dB
提供自动温度和电缆老化补偿
SPI 控制接口速率高达 3.3Mbps
具有 1Mbps 快速模式增强版的 I2C（主/从）
支持 7.1 多条 I2S（4 个数据）通道
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