SNLA426 june   2023 DS320PR1601 , DS320PR410

1.   1
2.   Abstract
3.   Trademarks
4. 1 Introduction
5. 2 PCIe Gen3, Gen4, and Gen5 Loss Budget
6. 3 Minimum Eye Width
7. 4 Cross Talk Mitigation
8. 5 Humidity and Temperature Insertion Loss
9. 6 Critical Signals
10. 7 General High-Speed Signal Routing
11. 8 PCB Grain and Fiber Weave Selection
12. 9 PCB Material Loss Budget
13. 10High-Speed Signal Trace Impedance
14. 11High-Speed Signal Trace Length Matching
15. 12Differential Trace Routing Guidelines
16. 13Differential-Inter-Pair Matching
17. 14Intra-pair Length Matching
18. 15Trace Bends
19. 16Minimum Differential Trace-To-Trace Distance
20. 17Serpentine Guidelines
21. 18High-Speed Differential Signal Quick Rules
22. 19High-Speed Differential Pair Reference Plane
23. 20Via Staggering
24. 21Via Stubs
25. 22Via Pads
26. 23Via Discontinuity Mitigation
27. 24Back-Drill Stubs
28. 25AC Coupling Capacitors Placement
29. 26AC Coupling Capacitor Physical Placement
30. 27Auxiliary Signal AC Match Termination
31. 28Suggested PCB Stack-ups
32. 29Summary
33. 30References

High-Speed PCB Layout for PCIe Gen 5