SNVU743 September 2020 LP875761-Q1
This technical reference manual can be used as a reference for the LP875761A-Q1 default register bits after OTP memory download. This technical reference manual does not provide information about the electrical characteristics, external components, package, or the functionality of the device. For this information and the full register map, refer to the LP875761-Q1 Four-Phase 3-MHz 1-V 16-A DC/DC Buck Converter With Integrated Switches data sheet.
Table 1-1 lists the main OTP settings for power rails. Table 2-1 lists the register bits loaded from OTP memory.
| Description | Bit Name | LP875761ARNFRQ1 Value | |
|---|---|---|---|
| Device identification | OTP configuration | OTP_ID | 23h |
| BUCK0, BUCK1, BUCK2, BUCK3 | Output voltage | N/A | 1000 mV |
| Enable, EN pin, or I2C register | EN_BUCK0, EN_PIN_CTRL0, BUCK0_EN_PIN_SELECT | EN1 | |
| Force PWM | N/A | Yes | |
| Force multiphase | N/A | Yes | |
| Peak current limit per phase | N/A | 5 A | |
| Maximum load current | N/A | 16 A | |
| Slew rate | N/A | 3.8 mV/µs | |
| Switching frequency | N/A | 3 MHz | |
| I2C address | N/A | 60h | |
The maximum total output capacitance (local + POL) per phase (BUCK0, BUCK1, BUCK2, and BUCK3) depends on the slew rate setting. Check the data sheet for the allowed capacitance value.