Loading [MathJax]/jax/output/SVG/fonts/TeX/fontdata.js
Menu
Product
Email
PDF
Order now
RM42L432 16- and 32-Bit RISC Flash Microcontroller
SPNS180B
September 2012 – June 2015
PRODUCTION DATA.
CONTENTS
SEARCH
RM42L432 16- and 32-Bit RISC Flash Microcontroller
1
Device Overview
1.1
Features
1.2
Applications
1.3
Description
1.4
Functional Block Diagram
2
Revision History
3
Device Comparison
4
Terminal Configuration and Functions
4.1
PZ QFP Package Pinout (100-Pin)
4.2
Terminal Functions
4.2.1
High-End Timer (N2HET)
4.2.2
Enhanced Quadrature Encoder Pulse Modules (eQEP)
4.2.3
General-Purpose Input/Output (GPIO)
4.2.4
Controller Area Network Interface Modules (DCAN1, DCAN2)
4.2.5
Multibuffered Serial Peripheral Interface (MibSPI1)
4.2.6
Standard Serial Peripheral Interface (SPI2)
4.2.7
Local Interconnect Network Controller (LIN)
4.2.8
Multibuffered Analog-to-Digital Converter (MibADC)
4.2.9
System Module
4.2.10
Error Signaling Module (ESM)
4.2.11
Main Oscillator
4.2.12
Test/Debug Interface
4.2.13
Flash
4.2.14
Core Supply
4.2.15
I/O Supply
4.2.16
Core and I/O Supply Ground Reference
4.3
Output Multiplexing and Control
4.3.1
Notes on Output Multiplexing
4.3.2
General Rules for Multiplexing Control Registers
4.4
Special Multiplexed Options
4.4.1
Filtering for eQEP Inputs
4.4.1.1
eQEPA Input
4.4.1.2
eQEPB Input
4.4.1.3
eQEPI Input
4.4.1.4
eQEPS Input
4.4.2
N2HET PIN_nDISABLE Input Port
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Power-On Hours (POH)
5.4
Recommended Operating Conditions
5.5
Switching Characteristics Over Recommended Operating Conditions for Clock Domains
5.6
Wait States Required
5.7
Power Consumption
5.8
Thermal Resistance Characteristics for PZ
5.9
Input/Output Electrical Characteristics
5.10
Output Buffer Drive Strengths
5.11
Input Timings
5.12
Output Timings
6
System Information and Electrical Specifications
6.1
Voltage Monitor Characteristics
6.1.1
Important Considerations
6.1.2
Voltage Monitor Operation
6.1.3
Supply Filtering
6.2
Power Sequencing and Power-On Reset
6.2.1
Power-Up Sequence
6.2.2
Power-Down Sequence
6.2.3
Power-On Reset: nPORRST
6.2.3.1
nPORRST Electrical and Timing Requirements
6.3
Warm Reset (nRST)
6.3.1
Causes of Warm Reset
6.3.2
nRST Timing Requirements
6.4
ARM Cortex-R4 CPU Information
6.4.1
Summary of ARM Cortex-R4 CPU Features
6.4.2
ARM Cortex-R4 CPU Features Enabled by Software
6.4.3
Dual Core Implementation
6.4.4
Duplicate clock tree after GCLK
6.4.5
ARM Cortex-R4 CPU Compare Module (CCM) for Safety
6.4.6
CPU Self-Test
6.4.6.1
Application Sequence for CPU Self-Test
6.4.6.2
CPU Self-Test Clock Configuration
6.4.6.3
CPU Self-Test Coverage
6.5
Clocks
6.5.1
Clock Sources
6.5.1.1
Main Oscillator
6.5.1.1.1
Timing Requirements for Main Oscillator
6.5.1.2
Low-Power Oscillator
6.5.1.2.1
Features
6.5.1.2.2
LPO Electrical and Timing Specifications
6.5.1.3
Phase Locked Loop (PLL) Clock Modules
6.5.1.3.1
Block Diagram
6.5.1.3.2
PLL Timing Specifications
6.5.2
Clock Domains
6.5.2.1
Clock Domain Descriptions
6.5.2.2
Mapping of Clock Domains to Device Modules
6.5.3
Clock Test Mode
6.6
Clock Monitoring
6.6.1
Clock Monitor Timings
6.6.2
External Clock (ECLK) Output Functionality
6.6.3
Dual Clock Comparator
6.6.3.1
Features
6.6.3.2
Mapping of DCC Clock Source Inputs
6.7
Glitch Filters
6.8
Device Memory Map
6.8.1
Memory Map Diagram
6.8.2
Memory Map Table
6.8.3
Master/Slave Access Privileges
6.9
Flash Memory
6.9.1
Flash Memory Configuration
6.9.2
Main Features of Flash Module
6.9.3
ECC Protection for Flash Accesses
6.9.4
Flash Access Speeds
6.10
Flash Program and Erase Timings for Program Flash
6.11
Flash Program and Erase Timings for Data Flash
6.12
Tightly Coupled RAM Interface Module
6.12.1
Features
6.12.2
TCRAMW ECC Support
6.13
Parity Protection for Accesses to peripheral RAMs
6.14
On-Chip SRAM Initialization and Testing
6.14.1
On-Chip SRAM Self-Test Using PBIST
6.14.1.1
Features
6.14.1.2
PBIST RAM Groups
6.14.2
On-Chip SRAM Auto Initialization
6.15
Vectored Interrupt Manager
6.15.1
VIM Features
6.15.2
Interrupt Request Assignments
6.16
Real-Time Interrupt Module
6.16.1
Features
6.16.2
Block Diagrams
6.16.3
Clock Source Options
6.17
Error Signaling Module
6.17.1
Features
6.17.2
ESM Channel Assignments
6.18
Reset / Abort / Error Sources
6.19
Digital Windowed Watchdog
6.20
Debug Subsystem
6.20.1
Block Diagram
6.20.2
Debug Components Memory Map
6.20.3
JTAG Identification Code
6.20.4
Debug ROM
6.20.5
JTAG Scan Interface Timings
6.20.6
Advanced JTAG Security Module
6.20.7
Boundary Scan Chain
7
Peripheral Information and Electrical Specifications
7.1
Peripheral Legend
7.2
Multibuffered 12-Bit Analog-to-Digital Converter
7.2.1
Features
7.2.2
Event Trigger Options
7.2.2.1
MIBADC Event Trigger Hookup
7.2.3
ADC Electrical and Timing Specifications
7.2.4
Performance (Accuracy) Specifications
7.2.4.1
MibADC Nonlinearity Errors
7.2.4.2
MibADC Total Error
7.3
General-Purpose Input/Output
7.3.1
Features
7.4
Enhanced High-End Timer (N2HET)
7.4.1
Features
7.4.2
N2HET RAM Organization
7.4.3
Input Timing Specifications
7.4.4
N2HET Checking
7.4.4.1
Output Monitoring using Dual Clock Comparator (DCC)
7.4.5
Disabling N2HET Outputs
7.4.6
High-End Timer Transfer Unit (N2HET)
7.4.6.1
Features
7.4.6.2
Trigger Connections
7.5
Controller Area Network (DCAN)
7.5.1
Features
7.5.2
Electrical and Timing Specifications
7.6
Local Interconnect Network Interface (LIN)
7.6.1
LIN Features
7.7
Multibuffered / Standard Serial Peripheral Interface
7.7.1
Features
7.7.2
MibSPI Transmit and Receive RAM Organization
7.7.3
MibSPI Transmit Trigger Events
7.7.3.1
MIBSPI1 Event Trigger Hookup
7.7.4
MibSPI/SPI Master Mode I/O Timing Specifications
7.7.5
SPI Slave Mode I/O Timings
7.8
Enhanced Quadrature Encoder (eQEP)
7.8.1
Clock Enable Control for eQEPx Modules
7.8.2
Using eQEPx Phase Error
7.8.3
Input Connections to eQEPx Modules
7.8.4
Enhanced Quadrature Encoder Pulse (eQEPx) Timing
8
Device and Documentation Support
8.1
Device Support
8.1.1
Development Support
8.1.1.1
Getting Started
8.1.2
Device Nomenclature
8.2
Documentation Support
8.2.1
Related Documentation from Texas Instruments
8.3
Community Resources
8.4
Trademarks
8.5
Electrostatic Discharge Caution
8.6
Glossary
8.7
Device Identification Code Register
8.8
Die Identification Registers
8.9
Module Certifications
8.9.1
DCAN Certification
8.9.2
LIN Certifications
8.9.2.1
LIN Master Mode
8.9.2.2
LIN Slave Mode - Fixed Baud Rate
8.9.2.3
LIN Slave Mode - Adaptive Baud Rate
9
Mechanical Packaging and Orderable Addendum
9.1
Packaging Information
IMPORTANT NOTICE
search
No matches found.
Full reading width
Full reading width
Comfortable reading width
Expanded reading width
Card for each section
Card with all content
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP
|
米乐app下载官网（中国）|ios|Android/通用版APP最新版
|
米乐|米乐·M6（中国大陆）官方网站
|
千亿体育登陆地址
|
华体会体育（中国）HTH·官方网站
|
千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载
|
18新利网v1.2.5|中国官方网站
|
bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】
|
千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装
|