ZHCSFS6B
July 2016 – June 2018
SN65DSI85-Q1
PRODUCTION DATA.
1
特性
2
应用
3
说明
典型应用
4
修订历史记录
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Reset Implementation
8.3.2
Initialization Setup
8.3.3
LVDS Output Formats
8.3.4
DSI Lane Merging
8.3.5
DSI Pixel Stream Packets
8.3.6
DSI Video Transmission Specifications
8.3.7
ULPS
8.3.8
LVDS Pattern Generation
8.4
Device Functional Modes
8.4.1
Operating Modes
8.5
Programming
8.5.1
Clock Configurations and Multipliers
8.6
Register Maps
8.6.1
Local I2C Interface Overview
8.6.1.1
Write Procedure
8.6.1.2
Read Procedure
8.6.1.3
Setting a Starting Sub-Address Procedure
8.6.2
Control and Status Registers Overview
8.6.3
CSR Bit
8.6.3.1
ID Registers (address = 0x00 to 0x08)
Table 7.
ID Register Field Descriptions
8.6.3.2
Reset and Clock Registers
8.6.3.2.1
Address 0x09
Table 8.
Address 0x09 Definitions
8.6.3.2.2
Address 0x0A
Table 9.
Address 0x0A Field Descriptions
8.6.3.2.3
Address 0x0B
Table 10.
Address 0x0B Field Descriptions
8.6.3.2.4
Address 0x0D
Table 11.
Address 0x0D Field Descriptions
8.6.3.3
DSI Registers
8.6.3.3.1
Address 0x10
Table 12.
Address 0x10 Field Descriptions
8.6.3.3.2
Address 0x11
Table 13.
Address 0x11 Field Descriptions
8.6.3.3.3
Address 0x12
Table 14.
Address 0x12 Field Descriptions
8.6.3.3.4
Address 0x13
Table 15.
Address 0x13 Field Descriptions
8.6.3.4
LVDS Registers
8.6.3.4.1
Address 0x18
Table 16.
Address 0x18 Field Descriptions
8.6.3.4.2
Address 0x19
Table 17.
Address 0x19 Field Descriptions
8.6.3.4.3
Address 0x1A
Table 18.
Address 0x1A Field Descriptions
8.6.3.4.4
Address 0x1B
Table 19.
Address 0x1B Field Descriptions
8.6.3.5
Video Registers
8.6.3.5.1
Address 0x20
Table 20.
Address 0x20 Field Descriptions
8.6.3.5.2
Address 0x21
Table 21.
Address 0x21 Field Descriptions
8.6.3.5.3
Address 0x22
Table 22.
Address 0x22 Field Descriptions
8.6.3.5.4
Address 0x23
Table 23.
Address 0x23 Field Descriptions
8.6.3.5.5
Address 0x24
Table 24.
Address 0x24 Field Descriptions
8.6.3.5.6
Address 0x25
Table 25.
Address 0x25 Field Descriptions
8.6.3.5.7
Address 0x26
Table 26.
Address 0x26 Field Descriptions
8.6.3.5.8
Address 0x27
Table 27.
Address 0x27 Field Descriptions
8.6.3.5.9
Address 0x28
Table 28.
Address 0x28 Field Descriptions
8.6.3.5.10
Address 0x29
Table 29.
Address 0x29 Field Descriptions
8.6.3.5.11
Address 0x2A
Table 30.
Address 0x2A Field Descriptions
8.6.3.5.12
Address 0x2B
Table 31.
Address 0x2B Field Descriptions
8.6.3.5.13
Address 0x2C
Table 32.
Address 0x2C Field Descriptions
8.6.3.5.14
Address 0x2D
Table 33.
Address 0x2D Field Descriptions
8.6.3.5.15
Address 0x2E
Table 34.
Address 0x2E Field Descriptions
8.6.3.5.16
Address 0x2F
Table 35.
Address 0x2F Field Descriptions
8.6.3.5.17
Address 0x30
Table 36.
Address 0x30 Field Descriptions
8.6.3.5.18
Address 0x31
Table 37.
Address 0x31 Field Descriptions
8.6.3.5.19
Address 0x32
Table 38.
Address 0x32 Field Descriptions
8.6.3.5.20
Address 0x33
Table 39.
Address 0x33 Field Descriptions
8.6.3.5.21
Address 0x34
Table 40.
Address 0x34 Field Descriptions
8.6.3.5.22
Address 0x35
Table 41.
Address 0x35 Field Descriptions
8.6.3.5.23
Address 0x36
Table 42.
Address 0x36 Field Descriptions
8.6.3.5.24
Address 0x37
Table 43.
Address 0x37 Field Descriptions
8.6.3.5.25
Address 0x38
Table 44.
Address 0x38 Field Descriptions
8.6.3.5.26
Address 0x39
Table 45.
Address 0x39 Field Descriptions
8.6.3.5.27
Address 0x3A
Table 46.
Address 0x3A Field Descriptions
8.6.3.5.28
Address 0x3B
Table 47.
Address 0x3B Field Descriptions
8.6.3.5.29
Address 0x3C
Table 48.
Address 0x3C Field Descriptions
8.6.3.5.30
Address 0x3D
Table 49.
Address 0x3D Field Descriptions
8.6.3.5.31
Address 0x3E
Table 50.
Address 0x3E Field Descriptions
8.6.3.6
IRQ Registers
8.6.3.6.1
Address 0xE0
Table 51.
Address 0xE0 Field Descriptions
8.6.3.6.2
Address 0xE1
Table 52.
Address 0xE1 Field Descriptions
8.6.3.6.3
Address 0xE2
Table 53.
Address 0xE2 Field Descriptions
8.6.3.6.4
Address 0xE5
Table 54.
Address 0xE5 Field Descriptions
8.6.3.6.5
Address 0xE6
Table 55.
Address 0xE6 Field Descriptions
9
Application and Implementation
9.1
Application Information
9.1.1
Video STOP and Restart Sequence
9.1.2
Reverse LVDS Pin Order Option
9.1.3
IRQ Usage
9.2
Typical Applications
9.2.1
Typical WUXGA 18-bpp Application
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.2.1
Example Script
9.2.1.3
Application Curve
9.2.2
Typical WQXGA 24-bpp Application
9.2.2.1
Design Requirements
10
Power Supply Recommendations
10.1
VCC Power Supply
10.2
VCORE Power Supply
11
Layout
11.1
Layout Guidelines
11.1.1
Package Specific
11.1.2
Differential pairs
11.1.3
Ground
11.2
Layout Example
12
器件和文档支持
12.1
文档支持
12.1.1
相关文档
12.2
接收文档更新通知
12.3
社区资源
12.4
商标
12.5
静电放电警告
12.6
术语表
13
机械、封装和可订购信息
1
特性
符合汽车类应用的 要求
具有符合 AEC-Q100 标准的下列特性：
器件温度等级 2：-40°C 至 105°C 的环境运行温度范围
器件 HBM ESD 分类等级 3A
器件 CDM ESD 分类等级 C6
实现了 MIPI D-PHY 版本 1.00.00 物理层前端和显示屏串行接口 (DSI) 版本 1.02.00
双通道 DSI 接收器在每个通道上可针对 1 条，2 条，3 条或 4 条 D-PHY 数据信道进行配置，每信道的运行速率高达 1Gbps
支持 RGB666 和 RGB888 格式的 18bpp 与 24bpp DSI 视频流
适合 60fps WQXGA 2560 × 1600 分辨率（18bpp 和 24bpp 颜色），以及 60fps（120fps 等效）WUXGA 1920 × 1200 分辨率和 3D 图形显示（24bpp 颜色）
MIPI 前端可配置为单通道或双通道 DSI 配置
针对单链路或双链路 LVDS 的输出配置
支持双通道 DSI ODD/EVEN 和 LEFT/RIGHT 操作模式
支持两个单通道 DSI 转两条单链路 LVDS 的操作模式
双链路或单链路模式下 LVDS 输出时钟范围为 25MHz 到 154MHz
LVDS 像素时钟可采用自由运行持续 D-PHY 时钟或外部基准时钟 (REFCLK)
1.8V 主 V
CC
电源
低功耗 特性 包括关断模式、低 LVDS 输出电压摆幅、共模以及 MIPI 超低功耗状态 (ULPS) 支持
针对简化印刷电路板 (PCB) 走线的 LVDS 通道交换 (SWAP)，LVDS 引脚顺序反向特性
采用 64 引脚 10mm × 10mm HTQFP (PAP) 封装 PowerPAD™IC 封装
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