The LM3489 device is a high-efficiency PFET switching regulator controller that can be used to quickly and easily develop a small, cost-effective, switching buck regulator for a wide range of applications. The hysteretic control architecture provides for simple design without any control loop stability concerns using a wide variety of external components. The PFET architecture also allows for low component count as well as ultra-low dropout, 100% duty cycle operation. Another benefit is high efficiency operation at light loads without an increase in output ripple. A dedicated enable pin provides a shutdown mode drawing only 7 µA. Leaving the enable pin unconnected defaults to on.
Current limit protection can be implemented by measuring the voltage across the PFET’s RDS(ON), thus eliminating the need for a sense resistor. A sense resistor may be used to improve current limit accuracy if desired. The cycle-by-cycle current limit can be adjusted with a single resistor, ensuring safe operation over a range of output currents.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LM3489 LM3489-Q1 |
VSSOP (8) | 3.00 mm × 3.00 mm |
Changes from B Revision (February 2013) to C Revision
Changes from A Revision (February 2013) to B Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | ISENSE | I | The current sense input pin. This pin must be connected to the PFET drain terminal directly or through a series resistor up to 600 Ω for 28 V > VIN > 35 V. |
2 | GND | — | Signal ground |
3 | EN | I | Enable pin. Connect EN pin to ground to shutdown the part or float to enable operation (Internally pulled high). This pin can also be used to perform UVLO function. |
4 | FB | I | The feedback input. Connect the FB to a resistor voltage divider between the output and GND for an adjustable output voltage. |
5 | ADJ | I | Current limit threshold adjustment. Connected to an internal 5.5-µA current source. A resistor is connected between this pin and VIN. The voltage across this resistor is compared with the ISENSE pin voltage to determine if an overcurrent condition has occurred. |
6 | PGND | — | Power ground |
7 | PGATE | O | Gate drive output for the external PFET. PGATE swings between VIN and VIN 5-V. |
8 | VIN | I | Power supply input pin |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VIN voltage | –0.3 | 36 | V | |
PGATE voltage | –0.3 | 36 | V | |
FB voltage | –0.3 | 5 | V | |
ISENSE voltage | –1 | 36 | V | |
–1 (<100 ns) | ||||
ADJ voltage | –0.3 | 36 | V | |
EN voltage(2) | –0.3 | 6 | V | |
Power dissipation, TA = 25°C(3) | 417 | mW | ||
Junction temperature, TJ | –40 | 150 | °C | |
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±750 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per AEC Q100-002(1) | ±2000 | V |
Charged device model (CDM), per AEC Q100-011 | ±750 |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VIN | Supply voltage | 4.5 | 35 | V | |
EN voltage(1) | 5.5 | V | |||
TJ | Operating junction temperature(2) | LM3489 | –40 | 125 | °C |
LM3489-Q1 | –40 | 150 | °C |
THERMAL METRIC(1) | LM3489 | UNIT | |
---|---|---|---|
DGK (VSSOP) | |||
8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 163.7 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 56.6 | °C/W |
RθJB | Junction-to-board thermal resistance | 83.3 | °C/W |
ψJT | Junction-to-top characterization parameter | 5.4 | °C/W |
ψJB | Junction-to-board characterization parameter | 82 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | — | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
ISHDN | Shutdown input supply current | EN = 0 V | 7 | 15 | µA | ||
VEN | Enable threshold voltage | Enable rising | 1.15 | 1.5 | 1.85 | V | |
VEN_HYST | Enable threshold hysteresis | 130 | mV | ||||
IQ | Quiescent current at ground pin | FB = 1.5 V (not switching) | 280 | 400 | µA | ||
VFB | Feedback voltage(1) | 1.214 | 1.239 | 1.264 | V | ||
VHYST | Comparator hysteresis | 10 | 20 | mV | |||
VCL_OFFSET | Current limit comparator offset | VFB = 1 V | –20 | 0 | 20 | mV | |
ICL_ADJ | Current limit ADJ current source | VFB = 1.5 V | 3 | 5.5 | 7 | µA | |
TCL | Current limit one-shot off-time | VADJ = 11.5 V, VISNS = 11 V, VFB = 1 V | 6 | 9 | 14 | µs | |
RPGATE | Driver resistance | Source, ISOURCE = 100 mA | 5.5 | Ω | |||
Sink, ISINK = 100 mA | 8.5 | ||||||
IPGATE | Driver output current | Source, VIN = 7 V, PGATE = 3.5 V | 0.44 | A | |||
Sink, VIN = 7 V, PGATE = 3.5 V | 0.1 | ||||||
IFB | FB pin bias current(2) | VFB = 1 V | 300 | 750 | nA | ||
TONMIN_NOR | Minimum ON time in normal operation | VISNS = VADJ + 0.1 V, Cload on OUT = 1000 pF(3) | 100 | ns | |||
TONMIN_CL | Minimum ON time in current limit | VISNS = VADJ – 0.1 V, VFB = 1 V, Cload on OUT = 1000 pF(3) |
200 | ns | |||
%VFB/ΔVIN | Feedback voltage line regulation | 4.5 V ≤ VIN ≤ 35 V | 0.01% | V |
The LM3489 is a buck (step-down) DC-DC controller that uses a hysteretic control scheme. The control comparator is designed with approximately 10 mV of hysteresis. In response to the voltage at the FB pin, the gate drive (PGATE pin) turns the external PFET on or off. When the inductor current is too high, the current limit protection circuit engages and turns the PFET off for approximately 9 µs.
Hysteretic control does not require an internal oscillator. Switching frequency depends on the external components and operating conditions. The operating frequency reduces at light loads resulting in excellent efficiency compared to other architectures.
The output voltage can be programmed by two external resistors. The output can be set in a wide range from 1.239 V (typical) to VIN.
When the FB input to the control comparator falls below the reference voltage (1.239 V), the output of the comparator switches to a low state. This results in the driver output, PGATE, pulling the gate of the PFET low and turning on the PFET. With the PFET on, the input supply charges COUT and supplies current to the load through the series path through the PFET and the inductor. Current through the Inductor ramps up linearly and the output voltage increases. As the FB voltage reaches the upper threshold, which is the internal reference voltage plus 10 mV, the output of the comparator changes from low to high, and the PGATE responds by turning the PFET off. As the PFET turns off, the inductor voltage reverses, the catch diode turns on, and the current through the inductor ramps down. Then, as the output voltage reaches the internal reference voltage again, the next cycle starts.
The LM3489 operates in discontinuous conduction mode at light-load current or continuous conduction mode at heavy-load current. In discontinuous conduction mode, current through the inductor starts at zero and ramps up to the peak then ramps down to zero. The next cycle starts when the FB voltage reaches the reference voltage. Until then, the inductor current remains zero and the output capacitor supplies the load. The operating frequency is lower and switching losses reduced. In continuous conduction mode, current always flows through the inductor and never ramps down to zero.
The output voltage (VOUT) can be programmed by 2 external resistors. It can be calculated with Equation 1.
The minimum output voltage ripple (VOUT_PP) can be calculated in the same way with Equation 2.
For example, with VOUT set to 3.3 V, VOUT_PP is 26.6 mV in Equation 3.
Operating frequency (F) is determined by knowing the input voltage, output voltage, inductor, VHYST, ESR (Equivalent Series Resistance) of output capacitor, and the delay. It can be approximately calculated using Equation 4.
where
It includes the LM3489 propagation delay time and the PFET delay time. The propagation delay is 90 ns typically (see Figure 20).
The operating frequency and output ripple voltage can also be significantly influenced by the speed up capacitor (Cff). Cff is connected in parallel with the high side feedback resistor, R1. The location of this capacitor is similar to where a phase lead capacitor would be located in a PWM control scheme. However it's effect on hysteretic operation is much different. Cff effectively shorts out R1 at the switching frequency and applies the full output ripple to the FB pin without dividing by the R2/R1 ratio. The end result is a reduction in output ripple and an increase in operating frequency. When adding Cff, calculate the formula above with α = 1. The value of Cff depend on the desired operating frequency and the value of R2. A good starting point is 470-pF ceramic at 100-kHz decreasing linearly with increased operating frequency. Also note that as the output voltage is programmed below 2.5 V, the effect of Cff will decrease significantly.
The LM3489 has a cycle-by-cycle current limit. Current limit is sensed across the VDS of the PFET or across an additional sense resistor. When current limit is activated, the LM3489 turns off the external PFET for a period of 9 µs (typical). The current limit is adjusted by an external resistor, RADJ.
The current limit circuit is composed of the ISENSE comparator and the one-shot pulse generator. The positive input of the ISENSE comparator is the ADJ pin. An internal 5.5-µA current sink creates a voltage across the external RADJ resistor. This voltage is compared to the voltage across the PFET or sense resistor. The ADJ voltage can be calculated with Equation 5.
where
The negative input of the ISENSE comparator is the ISENSE pin that must be connected to the drain of the external PFET. The inductor current is determined by sensing the VDS. It can be calculated with Equation 6.
The current limit is activated when the voltage at the ADJ pin exceeds the voltage at the ISENSE pin. The ISENSE comparator triggers the 9-µs one-shot pulse generator forcing the driver to turn the PFET off. The driver turns the PFET back on after 9 µs. If the current has not reduced below the set threshold, the cycle will repeat continuously.
A filter capacitor, CADJ, must be placed as shown in Figure 21. CADJ filters unwanted noise so that the ISENSE comparator will not be accidentally triggered. A value of 100 pF to 1 nF is recommended in most applications. Higher values can be used to create a soft-start function (see Start Up).
The current limit comparator has approximately 100 ns of blanking time. This ensures that the PFET is fully on when the current is sensed. However, under extreme conditions such as cold temperature, some PFETs may not fully turn on within the blanking time. In this case, the current limit threshold must be increased. If the current limit function is used, the on time must be greater than 100 ns. Under low duty cycle operation, the maximum operating frequency is limited by this minimum on-time.
During current limit operation, the output voltage drops significantly as does operating frequency. As the load current is reduced, the output returns to the programmed voltage. However, there is a current limit foldback phenomenon inherent in this current limit architecture (see Figure 22).
At high input voltages (> 28 V) increased undershoot at the switch node can cause an increase in the current limit threshold. To avoid this problem, a low Vf Schottky catch diode must be used (see Catch Diode Selection (D1)). Additionally, a resistor can be placed between the ISENSE pin and the switch node. Any value in the range of 220 Ω to 600 Ω is recommended.
The current limit circuit is active during start-up. During start-up, the PFET stays on until either the current limit or the feedback comparator is tripped
If the current limit comparator is tripped first, then take the the foldback characteristic into account. Start-up into full load may require a higher current limit set point or the load must be applied after start-up.
One problem with selecting a higher current limit is inrush current during start-up. Increasing the capacitance (CADJ) in parallel with RADJ results in a soft-start characteristic. CADJ and RADJ create an RC time constant forcing current limit to activate at a lower current. The output voltage will ramp more slowly when using this technique. There is example start-up plot for CADJ equal to 1 nF in Typical Characteristics. Lower values for CADJ will have little to no effect on soft-start.
The VDS of a PFET tends to vary significantly over temperature. This will result an equivalent variation in current limit. To improve current limit accuracy, an external sense resistor can be connected from VIN to the source of the PFET, as shown in Figure 23. The current sense resistor, RCS must have value comparable with RDSON of the PFET used, typically in the range of 50 mΩ to 200 mΩ. Equation 6 in Current Limit Operation can be used by replacing the RDSON with RCS.
When switching, the PGATE pin swings from VIN (off) to some voltage below VIN (on). How far the PGATE will swing depends on several factors including the capacitance, on-time, and input voltage.
PGATE voltage swing will increase with decreasing gate capacitance. Although PGATE voltage will typically be around VIN-5V, with very small gate capacitances, this value can increase to a typical maximum of VIN-8.3 V.
Additionally, PGATE swing voltage will increase as on-time increases. During long on-times, such as when operating at 100% duty cycle, the PGATE voltage will eventually fall to its maximum voltage of VIN-8.3 V (typical) regardless of the PFET gate capacitance.
The PGATE voltage will not fall below 0.4 V (typical). Therefore, when the input voltage falls below approximately 9 V, the PGATE swing voltage range is reduced. At an input voltage of 7 V, for instance, PGATE will swing from 7 V to a minimum of 0.4 V.
The undervoltage lockout (UVLO) function can be implemented as shown in Figure 24. By incorporating the feature of the internal enable threshold, the lockout level can be programmed through an external potential divider formed with R3 and R4. The input voltage information is detected and compared with the enable threshold and the device operation is inhibited when VIN drops below the preset UVLO level. The UVLO and hysteresis voltage can be calculated with Equation 7 and Equation 8.
where
The LM3489 can be remotely shutdown by forcing the enable pin to ground. With EN pin grounded, the internal blocks other than the enable logic are deactivated and the shutdown current of the device is lowered to only 7 µA (typical). Releasing the EN pin allows for normal operation to resume. The EN pin is internally pulled high with the voltage clamped at 8 V typical. For normal operation, this pin must be left open. In case an external voltage source is applied to this pin for enable control, the applied voltage must not exceed the maximum operating voltage level specified in this datasheet (that is 5.5 V).
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
Hysteretic control is a simple control scheme. However the operating frequency and other performance characteristics highly depend on external conditions and components. If either the inductance, output capacitance, ESR, VIN, or Cff is changed, there is a change in the operating frequency and output ripple. The best approach is to determine what operating frequency is desirable in the application and then begin with the selection of the inductor and COUT ESR.
The important parameters for the inductor are the inductance and the current rating. The LM3489 operates over a wide frequency range and can use a wide range of inductance values. A rule of thumb is to use the equations used for Simple Switchers®. The equations for inductor ripple (Δi) as a function of output current (IOUT) depend on Iout:
For Iout < 2 A, Δi ≤ Iout × Iout−0.366726.
For Iout > 2 A, Δi ≤ Iout × 0.3.
The inductance can be calculated with Equation 9 and Equation 10 based upon the desired operating frequency.
where
The inductor must be rated with Equation 11.
The inductance value and the resulting ripple is one of the key parameters controlling operating frequency. The second is the inductor ESR that contribute to the steady-state power loss due to current flowing through the inductor.
The ESR of the output capacitor times the inductor ripple current is equal to the output ripple of the regulator. However, the VHYST sets the first-order value of this ripple. As ESR is increased with a given inductance, operating frequency increases as well. If ESR is reduced then the operating frequency reduces.
The use of ceramic capacitors has become a common desire of many power supply designers. However, ceramic capacitors have a very low ESR resulting in a 90° phase shift of the output voltage ripple. This results in low operating frequency and increased output ripple. To fix this problem a low-value resistor must be added in series with the ceramic output capacitor. Although counter intuitive, this combination of a ceramic capacitor and external series resistance provides highly accurate control over the output voltage ripple. Other types capacitor, such as Sanyo POS CAP and OS-CON, Panasonic SP CAP, and Nichicon NA series, are also recommended and may be used without additional series resistance.
For all practical purposes, any type of output capacitor may be used with proper circuit verification.
A bypass capacitor is required between the input source and ground. It must be located near the source pin of the external PFET. The input capacitor prevents large voltage transients at the input and provides the instantaneous current when the PFET turns on.
The important parameters for the input capacitor are the voltage rating and the RMS current rating. Follow the manufacturer's recommended voltage derating. For high-input voltage applications, low-ESR electrolytic, Nichicon UD series or the Panasonic FK series are available. The RMS current in the input capacitor can be calculated with Equation 12.
The input capacitor power dissipation can be calculated with Equation 13.
The input capacitor must be able to handle the RMS current and the dissipation. Several input capacitors may be connected in parallel to handle large RMS currents. In some cases it may be much cheaper to use multiple electrolytic capacitors than a single low-ESR, high-performance capacitor such as OS-CON or Tantalum. The capacitance value must be selected such that the ripple voltage created by the switch current pulses is less than 10% of the total DC voltage across the capacitor.
For high VIN conditions (> 28 V), the fast switching, high swing of the internal gate drive introduces unwanted disturbance to the VIN rail and the current limit function can be affected. To eliminate this potential problem, a high-quality ceramic capacitor of 0.1 µF is recommended to filter out the internal disturbance at the VIN pin. This capacitor must be placed right next to the VIN pin for best performance.
The current limit is determined with Equation 14 by connecting a resistor (RADJ) between input voltage and the ADJ pin, pin 5.
where
Using the minimum value for ICL_ADJ (3 µA) ensures that the current limit threshold is set higher than the peak inductor current.
The RADJ value must be selected to ensure that the voltage at the ADJ pin does not fall below 3.5 V. With this in mind, RADJ_MAX = (VIN – 3.5) / 7 µA. If a larger RADJ value is needed to set the desired current limit, either use a PFET with a lower RDSON or use a current sense resistor as shown in Figure 23.
The current limit function can be disabled by connecting the ADJ pin to ground and ISENSE to VIN.
The important parameters for the catch diode are the peak current, the peak reverse voltage, and the average power dissipation. The average current through the diode can be calculated with Equation 15.
The off-state voltage across the catch diode is approximately equal to the input voltage. The peak reverse voltage rating must be greater than input voltage. In nearly all cases a Schottky diode is recommended. In low-output voltage applications, a low forward voltage provides improved efficiency. For high-temperature applications, diode leakage current may become significant and require a higher reverse voltage rating to achieve acceptable performance.
The important parameters for the PFET are the maximum Drain-Source voltage (VDS), the ON resistance (RDSON), Current rating, and the input capacitance.
The voltage across the PFET when it is turned off is equal to the sum of the input voltage and the diode forward voltage. The VDS must be selected to provide some margin beyond the input voltage.
PFET drain current, Id, must be rated higher than the peak inductor current, IIND-PEAK.
Depending on operating conditions, the PGATE voltage may fall as low as VIN – 8.3 V. Therefore, a PFET must be selected with a VGS maximum rating greater than the maximum PGATE swing voltage.
As input voltage decreases below 9 V, PGATE swing voltage may also decrease. At 5-V input the PGATE will swing from VIN to VIN – 4.6 V. To ensure that the PFET turns on quickly and completely, a low threshold PFET must be used when the input voltage is less than 7 V.
Total power loss in the FET can be approximated using Equation 16.
where
A value of 10 ns to 20 ns is typical for ton and toff.
A PFET must be selected with a turnon rise time of less than 100 ns. Slower rise times will degrade efficiency, can cause false current limiting, and in extreme cases may cause abnormal spiking at the PGATE pin.
The RDSON is used in determining the current limit resistor value, RADJ. Note that the RDSON has a positive temperature coefficient. At 100°C, the RDSON may be as much as 150% higher than the 25°C value. This increase in RDSON must be considered when determining RADJ in wide temperature range applications. If the current limit is set based upon 25°C ratings, then false current limiting can occur at high temperature.
Keeping the gate capacitance below 2000 pF is recommended to keep switching losses and transition times low. This will also help keep the PFET drive current low, which will improve efficiency and lower the power dissipation within the controller.
As gate capacitance increases, operating frequency must be reduced and as gate capacitance decreases operating frequency can be increased.
The enable pin is internally pulled high with clamping at 8 V typical. For normal operation this pin must be left open. To disable the device, the enable pin must be connected to ground externally. If an external voltage source is applied to this pin for enable control, the applied voltage must not exceed the maximum operating voltage level specified in this datasheet, that is 5.5 V. For most applications, an open-drain or open-collector transistor can be used to short this pin to ground to shutdown the device .
This device is designed to operate over a recommended input voltage supply range of 4.5 V to 35 V. The input supply must be well regulated. If the input supply is located far from the LM3485 EVM and needs a long power supply cable to connect, an additional bulk capacitor may be required. An electrolytic capacitor with a value of
47 µF can be used typically.
As mentioned in Current Limit Operation, at higher input voltages (> 28 V) an increased negative SW transient spike at the switch node can lead to an increase in the current limit threshold due to the formation of the parasitic NPN connection between the ISENSE pin, the internal substrate and the ADJ pin . To avoid this issue, a Schottky catch diode with lower forward voltage drop must be used. In addition to that, a resistor must be placed between the ISENSE pin and the external switch node. A resistor value in the range of 220 Ω to 600 Ω is recommended.
The PCB layout is very important in all switching regulator designs. Poor layout can cause switching noise into the feedback signal and generate EMI problems. For minimal inductance, the wires indicated by heavy lines in schematic diagram must be as wide and short as possible. Keep the ground pin of the input capacitor as close as possible to the anode of the catch diode. This path carries a large AC current. The switching node, the node with the diode cathode, inductor and FET drain must be kept short. This node is one of the main sources for radiated EMI since it sees a large AC voltage at the switching frequency. It is always a good practice to use a ground plane in the design, particularly for high-current applications.
The two ground pins, PGND and GND, must be connected by as short a trace as possible. They can be connected underneath the device. These pins are resistively connected internally by approximately 50 Ω. The ground pins must be tied to the ground plane, or to a large ground trace in close proximity to both the FB divider and COUT grounds.
The gate pin of the external PFET must be placed close to the PGATE pin. However, if a very small FET is used, a resistor may be required between PGATE pin and the gate of the PFET to reduce high-frequency ringing. Because this resistor will slow down the PFET’s rise time, the current limit blanking time must be taken into consideration (see Current Limit Operation). The feedback voltage signal line can be sensitive to noise. Avoid inductive coupling with the inductor or the switching node. The FB trace must be kept away from those areas. Also, the orientation of the inductor can contribute un-wanted noise coupling to the FB path. If noise problems are observed it may be worth trying a different orientation of the inductor and select the best for final component placement.
SPACE
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PARTS | PRODUCT FOLDER | SAMPLE & BUY | TECHNICAL DOCUMENTS | TOOLS & SOFTWARE | SUPPORT & COMMUNITY |
---|---|---|---|---|---|
LM3489 | Click here | Click here | Click here | Click here | Click here |
LM3489-Q1 | Click here | Click here | Click here | Click here | Click here |
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