LM5118-Q1 宽电压范围降压/升压控制器
- ZHCSGG9 June 2017 LM5118-Q1
  
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LM5118-Q1 宽电压范围降压/升压控制器

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

符合 AEC-Q100 的汽车应用标准
- 器件温度 1 级：-40°C 至 +125°C 的环境运行温度范围
- 器件 HBM ESD 分类等级 2
- 器件组件充电模式 (CDM) ESD 分类等级 C6
3V 至 75V 的超宽输入电压范围
仿真峰值电流模式控制
在降压和升压模式之间平滑转换
开关频率最高可通过编程设定为 500kHz
振荡器同步功能
内部高电压偏置稳压器
集成了高侧和低侧栅极驱动器
可编程软启动时间
超低关断电流
使能输入宽带宽误差放大器
1.5% 反馈基准精度
热关断
封装：20 引脚 HTSSOP（裸露焊盘）
结合使用 LM5118-Q1 和 WEBENCH® 电源设计器创建定制设计

2 应用

车用信息娱乐
汽车启动和停止系统
工业降压/升压电源

3 说明

LM5118-Q1 宽电压范围降压/升压开关稳压控制器具有使用最少外部组件实现高性能且具成本效益的降压/升压稳压器所需的所有功能。当输入电压低于或高于输出电压时，降压/升压拓扑可使输出电压保持稳定，因此，这款器件非常适合汽车应用。当输入电压比调节后的输出电压足够大时，LM5118-Q1 将作为降压稳压器运行，然后随着输入电压接近输出电压逐渐过渡到相应的降压/升压模式。这种双模式方法可在宽输入电压范围内保持稳压，并且在降压模式下提供最佳的转换效率，同时在模式转换期间提供无干扰的输出。该控制器易于使用，其中包含适用于高侧降压 MOSFET 和低侧升压 MOSFET 的驱动器。此稳压器控制方法基于采用仿真电流斜坡的电流模式控制。仿真电流模式控制可降低脉宽调制电路的噪声敏感度，以便可靠地控制高输入电压应用中所需的极小占空比。额外保护功能包括电流限制、热关断和使能输入。该器件采用功耗增强型 20 引脚 HTSSOP 封装，并且配有利于散热的裸露芯片连接焊盘。

器件信息⁽¹⁾

器件型号	封装	封装尺寸（标称值）
LM5118-Q1	HTSSOP (20)	6.50mm x 4.40mm

如需了解所有可用封装，请参阅数据表末尾的可订购米6体育平台手机版_好二三四附录。

简化电路原理图

效率与输入电压和输出电流（输出电压 = 12V）

4 修订历史记录

日期	修订版本	说明
2017 年 6 月	*	初始发行版。将 SNVS566 中的汽车器件移到了单独的米6体育平台手机版_好二三四说明书中

5 Pin Configuration and Functions

PWP Package

20-Pin HTSSOP

(Top View)

Pin Descriptions

PIN		TYPE⁽¹⁾	DESCRIPTION
NO.	NAME	TYPE⁽¹⁾	DESCRIPTION
1	VIN	P/I	Input supply voltage.
2	UVLO	I	If the UVLO pin is below 1.23 V, the regulator will be in standby mode (VCC regulator running, switching regulator disabled). When the UVLO pin exceeds 1.23 V, the regulator enters the normal operating mode. An external voltage divider can be used to set an undervoltage shutdown threshold. A fixed 5-µA current is sourced out of the UVLO pin. If a current limit condition exists for 256 consecutive switching cycles, an internal switch pulls the UVLO pin to ground and then releases.
3	RT	I	The internal oscillator frequency is set with a single resistor between this pin and the AGND pin. The recommended frequency range is 50 kHz to 500 kHz.
4	EN	I	If the EN pin is below 0.5 V, the regulator will be in a low power state drawing less than 10 µA from VIN. EN must be raised above 3 V for normal operation.
5	RAMP	I	Ramp control signal. An external capacitor connected between this pin and the AGND pin sets the ramp slope used for emulated current mode control.
6	AGND	G	Analog ground.
7	SS	I	Soft Start. An external capacitor and an internal 10-µA current source set the rise time of the error amp reference. The SS pin is held low when VCC is less than the VCC undervoltage threshold (< 3.7 V), when the UVLO pin is low (< 1.23 V), when EN is low (< 0.5 V) or when thermal shutdown is active.
8	FB	I	Feedback signal from the regulated output. Connect to the inverting input of the internal error amplifier.
9	COMP	O	Output of the internal error amplifier. The loop compensation network should be connected between COMP and the FB pin.
10	VOUT	I	Output voltage monitor for emulated current mode control. Connect this pin directly to the regulated output.
11	SYNC	I	Sync input for switching regulator synchronization to an external clock.
12	CS	I	Current sense input. Connect to the diode side of the current sense resistor.
13	CSG	I	Current sense ground input. Connect to the ground side of the current sense resistor.
14	PGND	G	Power Ground.
15	LO	O	Boost MOSFET gate drive output. Connect to the gate of the external boost MOSFET.
16	VCC	P/I/O	Output of the bias regulator. Locally decouple to PGND using a low ESR/ESL capacitor located as close to the controller as possible.
17	VCCX	P/I	Optional input for an externally supplied bias supply. If the voltage at the VCCX pin is greater than 3.9 V, the internal VCC regulator is disabled and the VCC pin is internally connected to VCCX pin supply. If VCCX is not used, connect to AGND.
18	HB	I	High-side gate driver supply used in bootstrap operation. The bootstrap capacitor supplies current to charge the high-side MOSFET gate. This capacitor should be placed as close to the controller as possible and connected between HB and HS.
19	HO	O	Buck MOSFET gate drive output. Connect to the gate of the high-side buck MOSFET through a short, low inductance path.
20	HS	I	Buck MOSFET source pin. Connect to the source terminal of the high-side buck MOSFET and the bootstrap capacitor.
—	EP	—	Solder to the ground plane under the IC to aid in heat dissipation.

(1) G = Ground, I = Input, O = Output, P = Power

6 Specifications

6.1 Absolute Maximum Ratings

over operating free air temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
VIN, EN, VOUT to GND	–0.3	76	V
VCC, LO, VCCX, UVLO to GND	–0.3	15	V
HB to HS	–0.3	15	V
HO to HS	–0.3	HB + 0.3	V
HS to GND	–4	76	V
CSG, CS to GND	–0.3	0.3	V
RAMP, SS, COMP, FB, SYNC, RT to GND	–0.3	7	V
Junction temperature	–40	150	°C
Storage temperature, T_stg	–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011	±1000	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free air temperature range (unless otherwise noted)⁽⁴⁾

	MIN	MAX	UNIT
VIN ⁽²⁾	3	75	V
VCC, VCCX	4.75	14	V
Junction temperature	–40	+125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LM5118-Q1	UNIT
		PWP (HTSSOP)
		20 PINS
R_θJA	Junction-to-ambient thermal resistance	40	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	4	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

Unless otherwise specified, the following conditions apply: VIN = 48 V, VCCX = 0 V, EN = 5 V, RT = 29.11 kΩ, No load on LO and HO. Typical values apply for T_J = 25°C; minimum and maximum values apply over the full junction temperature range for operation, −40°C to +125°C.⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
VIN SUPPLY
I_BIAS	VIN operating current	VCCX = 0 V		4.5	5.5	mA
I_BIASX	VIN operating current	VCCX = 5 V		1	1.85	mA
I_STDBY	VIN shutdown current	EN = 0 V		1	10	µA
VCC REGULATOR
V_CC(REG)	VCC regulation	VCCX = 0 V	6.8	7	7.2	V
V_CC(REG)	VCC regulation	VCCX = 0 V, VIN = 6 V	5	5.25	5.5	V
	VCC sourcing current limit	VCC = 0	21	35		mA
	VCCX switch threshold	VCCX rising	3.68	3.85	4.02	V
	VCCX switch hysteresis			0.2		V
	VCCX switch RDS(ON)	ICCX = 10 mA		5	12	Ω
	VCCX switch leakage	VCCX = 0 V		0.5	1	µA
	VCCCX pulldown resistance	VCCX = 3 V		70		kΩ
	VCC undervoltage lockout voltage	VCC rising	3.52	3.7	3.86	V
	VCC undervoltage hysteresis			0.21		V
	HB DC bias current	HB-HS = 15 V		205	260	µA
	VC LDO mode turnoff			10		V
EN INPUT
V_{IL max}	EN input low threshold				0.5	V
V_{IH min}	EN input high threshold		3			V
	EN input bias current	VEN = 3 V	–1		1	µA
	EN input bias current	VEN = 0.5 V	–1		1	µA
	EN input bias current	VEN = 75 V		50		µA
UVLO THRESHOLDS
	UVLO standby threshold	UVLO rising	1.191	1.231	1.271	V
	UVLO threshold hysteresis			0.105		V
	UVLO pullup current source	UVLO = 0 V		5		µA
	UVLO pulldown R_DS(ON)			100	200	Ω
SOFT START
	SS current source	SS = 0V	7.5	10.5	13.5	µA
	SS to FB offset	FB = 1.23 V		150		mV
	SS output low voltage	Sinking 100 µA, UVLO = 0 V		7		mV
ERROR AMPLIFIER
V_REF	FB reference voltage	Measured at FB pin, FB = COMP	1.212	1.23	1.248	V
	FB input bias current	FB = 2 V		20	200	nA
	COMP sink/source current		3			mA
A_OL	DC gain			80		dB
f_BW	Unity bain bandwidth			3		MHz
PWM COMPARATORS
t_HO(OFF)	Forced HO off-time		305	400	495	ns
T_ON(MIN)	Minimum HO on-time			70		ns
	COMP to comparator offset			200		mV
OSCILLATOR (RT PIN)
f_SW1	Frequency 1	RT = 29.11 kΩ	178	200	224	kHz
f_SW2	Frequency 2	RT = 9.525 kΩ	450	515	575	kHz
SYNC
	Sync threshold falling			1.3		V
CURRENT LIMIT
V_CS(TH)	Cycle-by-cycle sense voltage threshold (CS-CSG)	RAMP = 0 buck mode	–103	–125	–147	mV
V_CS(THX)	Cycle-by-cycle sense voltage threshold (CS-CSG)	RAMP = 0 buck-boost mode	–218	–255	–300	mV
	CS bias current	CS = 0 V		45	60	µA
	CSG bias current	CSG = 0 V		45	60	µA
	Current limit fault timer			256		cycles
RAMP GENERATOR
I_R1	RAMP current 1	VIN = 60 V, VOUT = 10 V	245	305	365	µA
I_R2	RAMP current 2	VIN = 12 V, VOUT = 12 V	95	115	135	µA
I_R3	RAMP current 3	VIN = 5 V, VOUT = 12 V	65	80	95	µA
	VOUT bias current	VOUT = 48 V		245		µA
LOW-SIDE (LO) GATE DRIVER
V_OLL	LO low-state output voltage	I_LO = 100 mA		0.14	0.23	V
V_OHL	LO high-state output voltage	I_LO = -100 mA V_OHL = V_CC-V_LO		0.25		V
	LO rise time	C-load = 1 nF, VCC = 8 V		16		ns
	LO fall time	C-load = 1 nF, VCC = 8 V		14		ns
I_OHL	Peak LO source current	V_LO = 0 V, VCC = 8 V		2.2		A
I_OLL	Peak LO sink current	V_LO = VCC = 8 V		2.7		A
HIGH-SIDE (HO) GATE DRIVER
V_OLH	HO low-state output voltage	I_HO = 100 mA		0.135	0.21	V
V_OHH	HO high-state output voltage	I_HO = -100 mA, V_OHH = V_HB-V_OH		0.25		V
	HO rise time	C-load = 1 nF, VCC = 8 V		14		ns
	HO fall time	C-load = 1 nF, VCC = 8 V		12		ns
I_OHH	Peak HO source current	V_HO = 0V, VCC = 8 V		2.2		A
I_OLH	Peak HO sink current	V_HO = VCC = 8 V		3.5		A
	HB-HS undervoltage lockout			3		V
BUCK-BOOST CHARACTERISTICS
	Buck-boost mode	Buck duty cycle ⁽³⁾	69%	75%	80%
THERMAL
T_SD	Thermal shutdown temperature			165		°C
	Thermal shutdown hysteresis			25		°C

(1) Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

(2) 5-V VIN is required to initially start the controller.

(3) When the duty cycle exceeds 75%, the LM5118-Q1 controller gradually phases into the Buck-Boost mode.

(4) The Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but does not ensure specific performance limits. For specifications and test conditions see Electrical Characteristics.

6.6 Typical Characteristics

Figure 1. Efficiency vs VIN and IOUT, VOUT = 12 V

Figure 3. VCC vs VIN

Figure 5. Error Amplifier Gain/Phase

Figure 7. Oscillator Frequency vs RT

Figure 2. Current Limit Threshold vs VOUT/VIN
VOUT = 12 V

Figure 4. VCC vs IVCC

Figure 6. LO and HO Peak Gate Current vs Output Voltage
VCC = 8 V