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LMK0480x Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
SNAS489K
March 2011 – December 2014
LMK04803
,
LMK04805
,
LMK04806
,
LMK04808
PRODUCTION DATA.
CONTENTS
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LMK0480x Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Typical Characteristics: Clock Output AC Characteristics
7
Parameter Measurement Information
7.1
Charge Pump Current Specification Definitions
7.1.1
Charge Pump Output Current Magnitude Variation Vs. Charge Pump Output Voltage
7.1.2
Charge Pump Sink Current Vs. Charge Pump Output Source Current Mismatch
7.1.3
Charge Pump Output Current Magnitude Variation vs. Ambient Temperature"Temperature" to "Ambient Temperature" in heading titled "Charge Pump Output Current Magnitude Variation vs. Ambient Temperature"
7.2
Differential Voltage Measurement Terminology
8
Detailed Description
8.1
Overview
8.1.1
System Architecture
8.1.2
PLL1 Redundant Reference Inputs (CLKin0/CLKin0* and CLKin1/CLKin1*)
8.1.3
PLL1 Tunable Crystal Support
8.1.4
VCXO/CRYSTAL Buffered Outputs
8.1.5
Frequency Holdover
8.1.6
Integrated Loop Filter Poles
8.1.7
Internal VCO
8.1.8
External VCO Mode
8.1.9
Clock Distribution
8.1.9.1
CLKout DIVIDER
8.1.9.2
CLKout Delay
8.1.9.3
Programmable Output Type
8.1.9.4
Clock Output Synchronization
8.1.10
0-Delay
8.1.11
Default Startup Clocks
8.1.12
Status Pins
8.1.13
Register Readback
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Serial MICROWIRE Timing Diagram
8.3.2
Advanced MICROWIRE Timing Diagrams
8.3.2.1
Three Extra Clocks or Double Program
8.3.2.2
Three Extra Clocks with LEuWire High
8.3.2.3
Readback
8.3.3
Inputs / Outputs
8.3.3.1
PLL1 Reference Inputs (CLKin0 and CLKin1)
8.3.3.2
PLL2 OSCin / OSCin* Port
8.3.3.3
Crystal Oscillator
8.3.4
Input Clock Switching
8.3.4.1
Input Clock Switching - Manual Mode
8.3.4.2
Input Clock Switching - Pin Select Mode
8.3.4.2.1
Pin Select Mode and Host
8.3.4.2.2
Switch Event without Holdover
8.3.4.2.3
Switch Event with Holdover
8.3.4.3
Input Clock Switching - Automatic Mode
8.3.4.3.1
Starting Active Clock
8.3.4.3.2
Clock Switch Event: PLL1 DLD
8.3.4.3.3
Clock Switch Event: PLL1 Vtune Rail
8.3.4.3.4
Clock Switch Event with Holdover
8.3.4.4
Input Clock Switching - Automatic Mode with Pin Select
8.3.4.4.1
Starting Active Clock
8.3.4.4.2
Clock Switch Event: PLL1 DLD
8.3.4.4.3
Clock Switch Event: PLL1 Vtune Rail
8.3.4.4.4
Clock Switch Event with Holdover -- revised text in Clock Switch Event with Holdover section
8.3.5
Holdover Mode
8.3.5.1
Enable Holdover
8.3.5.2
Entering Holdover
8.3.5.3
During Holdover
8.3.5.4
Exiting Holdover
8.3.5.5
Holdover Frequency Accuracy and DAC Performance
8.3.5.6
Holdover Mode - Automatic Exit of Holdover
8.3.6
PLLs
8.3.6.1
PLL1
8.3.6.2
PLL2
8.3.6.2.1
PLL2 Frequency Doubler
8.3.6.3
Digital Lock Detect
8.3.7
Status Pins
8.3.7.1
Logic Low
8.3.7.2
Digital Lock Detect
8.3.7.3
Holdover Status
8.3.7.4
DAC
8.3.7.5
PLL Divider Outputs
8.3.7.6
CLKinX_LOS
8.3.7.7
CLKinX Selected
8.3.7.8
MICROWIRE Readback
8.3.8
VCO
8.3.9
Clock Distribution
8.3.9.1
Fixed Digital Delay
8.3.9.2
Fixed Digital Delay - Example
8.3.9.3
Clock Output Synchronization (SYNC)
8.3.9.3.1
Effect of SYNC
8.3.9.3.2
Methods of Generating SYNC
8.3.9.3.3
Avoiding Clock Output Interruption Due to Sync
8.3.9.3.4
SYNC Timing
8.3.9.3.5
Dynamically Programming Digital Delay
8.3.9.3.5.1
Absolute vs. Relative Dynamic Digital Delay
8.3.9.3.5.2
Dynamic Digital Delay and 0-Delay Mode
8.3.9.3.5.3
SYNC and Minimum Step Size
8.3.9.3.5.4
Programming Overview
8.3.9.3.5.5
Internal Dynamic Digital Delay Timing
8.3.9.3.5.6
Other Timing Requirements
8.3.9.3.5.7
Absolute Dynamic Digital Delay
8.3.9.3.5.7.1
Absolute Dynamic Digital Delay - Example
8.3.9.3.5.8
Relative Dynamic Digital Delay
8.3.9.3.5.8.1
Relative Dynamic Digital Delay - Example
8.3.10
0-Delay Mode
8.4
Device Functional Modes
8.4.1
Mode Selection
8.4.2
Operating Modes
8.4.2.1
Dual PLL
8.4.2.2
0-Delay Dual PLL
8.4.2.3
Single PLL
8.4.2.4
0-Delay Single PLL
8.4.2.5
Clock Distribution
8.4.2.6
Mode 15 Additional Configurations
8.5
Programming
8.5.1
Special Programming Case for R0 to R5 for CLKoutX_Y_DIV and CLKoutX_Y_DDLY
8.5.1.1
Example
8.5.2
Recommended Programming Sequence
8.5.2.1
Overview
8.5.3
Readback
8.5.3.1
Readback - Example
8.6
Register Maps
8.6.1
Register Map and Readback Register Map
8.6.2
Default Device Register Settings After Power On Reset
8.6.3
Register Descriptions
8.6.3.1
Register R0 TO R5
8.6.3.1.1
CLKoutX_Y_PD, Powerdown CLKoutX_Y Output Path
8.6.3.1.2
CLKoutX_Y_OSCin_Sel, Clock Group Source
8.6.3.1.3
CLKoutY_ADLY_SEL[29], CLKoutX_ADLY_SEL[28], Select Analog Delay
8.6.3.1.4
CLKoutX_Y_DDLY, Clock Channel Digital Delay
8.6.3.1.5
Reset
8.6.3.1.6
POWERDOWN
8.6.3.1.7
CLKoutX_Y_HS, Digital Delay Half Shift
8.6.3.1.8
CLKoutX_Y_DIV, Clock Output Divide
8.6.3.2
Registers R6 TO R8
8.6.3.2.1
CLKoutX_TYPE
8.6.3.2.2
CLKoutX_Y_ADLY
8.6.3.3
Register R10
8.6.3.3.1
OSCout1_LVPECL_AMP, LVPECL Output Amplitude Control
8.6.3.3.2
OSCout0_TYPE
8.6.3.3.3
EN_OSCoutX, OSCout Output Enable
8.6.3.3.4
OSCoutX_MUX, Clock Output Mux
8.6.3.3.5
PD_OSCin, OSCin Powerdown Control
8.6.3.3.6
OSCout_DIV, Oscillator Output Divide
8.6.3.3.7
VCO_MUX
8.6.3.3.8
EN_FEEDBACK_MUX
8.6.3.3.9
VCO_DIV, VCO Divider
8.6.3.3.10
FEEDBACK_MUX
8.6.3.4
Register R11
8.6.3.4.1
MODE: Device Mode
8.6.3.4.2
EN_SYNC, Enable Synchronization
8.6.3.4.3
NO_SYNC_CLKoutX_Y
8.6.3.4.4
SYNC_MUX
8.6.3.4.5
SYNC_QUAL
8.6.3.4.6
SYNC_POL_INV
8.6.3.4.7
SYNC_EN_AUTO
8.6.3.4.8
SYNC_TYPE
8.6.3.4.9
EN_PLL2_XTAL
8.6.3.5
Register R12
8.6.3.5.1
LD_MUX
8.6.3.5.2
LD_TYPE
8.6.3.5.3
SYNC_PLLX_DLD
8.6.3.5.4
EN_TRACK
8.6.3.5.5
HOLDOVER_MODE
8.6.3.6
Register R13
8.6.3.6.1
HOLDOVER_MUX
8.6.3.6.2
HOLDOVER_TYPE
8.6.3.6.3
Status_CLKin1_MUX
8.6.3.6.4
Status_CLKin0_TYPE
8.6.3.6.5
DISABLE_DLD1_DET
8.6.3.6.6
Status_CLKin0_MUX
8.6.3.6.7
CLKin_SELECT_MODE
8.6.3.6.8
CLKin_Sel_INV
8.6.3.6.9
EN_CLKinX
8.6.3.7
Register 14
8.6.3.7.1
LOS_TIMEOUT
8.6.3.7.2
EN_LOS
8.6.3.7.3
Status_CLKin1_TYPE
8.6.3.7.4
CLKinX_BUF_TYPE, PLL1 CLKinX/CLKinX* Buffer Type
8.6.3.7.5
DAC_HIGH_TRIP
8.6.3.7.6
DAC_LOW_TRIP
8.6.3.7.7
EN_VTUNE_RAIL_DET
8.6.3.8
REGISTER 15
8.6.3.8.1
MAN_DAC
8.6.3.8.2
EN_MAN_DAC
8.6.3.8.3
HOLDOVER_DLD_CNT
8.6.3.8.4
FORCE_HOLDOVER
8.6.3.9
Register 16
8.6.3.9.1
XTAL_LVL
8.6.3.10
Register 23
8.6.3.10.1
DAC_CNT
8.6.3.11
Register 24
8.6.3.11.1
PLL2_C4_LF, PLL2 Integrated Loop Filter Component
8.6.3.11.2
PLL2_C3_LF, PLL2 Integrated Loop Filter Component
8.6.3.11.3
PLL2_R4_LF, PLL2 Integrated Loop Filter Component
8.6.3.11.4
PLL2_R3_LF, PLL2 Integrated Loop Filter Component
8.6.3.11.5
PLL1_N_DLY
8.6.3.11.6
PLL1_R_DLY
8.6.3.11.7
PLL1_WND_SIZE
8.6.3.12
Register 25
8.6.3.12.1
DAC_CLK_DIV
8.6.3.12.2
PLL1_DLD_CNT
8.6.3.13
Register 26
8.6.3.13.1
PLL2_WND_SIZE
8.6.3.13.2
EN_PLL2_REF_2X, PLL2 Reference Frequency Doubler
8.6.3.13.3
PLL2_CP_POL, PLL2 Charge Pump Polarity
8.6.3.13.4
PLL2_CP_GAIN, PLL2 Charge Pump Current
8.6.3.13.5
PLL2_DLD_CNT
8.6.3.13.6
PLL2_CP_TRI, PLL2 Charge Pump TRI-STATE
8.6.3.14
REGISTER 27
8.6.3.14.1
PLL1_CP_POL, PLL1 Charge Pump Polarity
8.6.3.14.2
PLL1_CP_GAIN, PLL1 Charge Pump Current
8.6.3.14.3
CLKinX_PreR_DIV
8.6.3.14.4
PLL1_R, PLL1 R Divider
8.6.3.14.5
PLL1_CP_TRI, PLL1 Charge Pump TRI-STATE
8.6.3.15
Register 28
8.6.3.15.1
PLL2_R, PLL2 R Divider
8.6.3.15.2
PLL1_N, PLL1 N Divider
8.6.3.16
Register 29
8.6.3.16.1
OSCin_FREQ, PLL2 Oscillator Input Frequency Register
8.6.3.16.2
PLL2_FAST_PDF, High PLL2 Phase Detector Frequency
8.6.3.16.3
PLL2_N_CAL, PLL2 N Calibration Divider
8.6.3.17
Register 30
8.6.3.17.1
PLL2_P, PLL2 N Prescaler Divider
8.6.3.17.2
PLL2_N, PLL2 N Divider
8.6.3.18
Register 31
8.6.3.18.1
READBACK_LE
8.6.3.18.2
READBACK_ADDR
8.6.3.18.3
uWire_LOCK
9
Application and Implementation
9.1
Application Information
9.1.1
Loop Filter
9.1.1.1
PLL1
9.1.1.2
PLL2
9.1.2
Driving CLKin and OSCin Inputs
9.1.2.1
Driving CLKin Pins with a Differential Source
9.1.2.2
Driving CLKin Pins with a Single-Ended Source
9.1.3
Termination and Use of Clock Output (Drivers)
9.1.3.1
Termination for DC Coupled Differential Operation
9.1.3.2
Termination for AC Coupled Differential Operation
9.1.3.3
Termination for Single-Ended Operation
9.1.4
Frequency Planning with the LMK0480x Family
9.1.5
PLL Programming
9.1.5.1
Example PLL2 N Divider Programming
9.1.5.1.1
Example PLL2 N Divider Programming
9.1.6
Digital Lock Detect Frequency Accuracy
9.1.6.1
Minimum Digital Lock Detect Time Calculation Example
9.1.7
Calculating Dynamic Digital Delay Values for any Divide
9.1.7.1
Example
9.1.8
Optional Crystal Oscillator Implementation (OSCin/OSCin*)
9.1.9
Application Curves
9.2
Typical Applications
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Device Selection
9.2.2.1.1
Clock Architect
9.2.2.1.2
Clock Design Tool
9.2.2.1.3
Calculation Using LCM
9.2.2.2
Device Configuration
9.2.2.2.1
PLL LO Reference
9.2.2.2.2
POR Clock
9.2.2.3
PLL Loop Filter Design
9.2.2.3.1
PLL1 Loop Filter Design
9.2.2.3.2
PLL2 Loop Filter Design
9.2.2.4
Clock Output Assignment
9.2.2.5
Other Device Specific Configuration
9.2.2.5.1
Digital Lock Detect
9.2.2.5.2
Holdover
9.2.2.6
Device Programming
9.2.3
Application Curve
9.3
System Examples
9.3.1
System Level Diagram
9.4
Do's and Don'ts
9.4.1
LVCMOS Complementary vs. Non-Complementary Operation
9.4.2
LVPECL Outputs
10
Power Supply Recommendations
10.1
Pin Connection Recommendations
10.1.1
Vcc Pins and Decoupling
10.1.1.1
Vcc2, Vcc3, Vcc10, Vcc11, Vcc12, Vcc13 (CLKout Vccs)
10.1.1.2
Vcc1 (VCO), Vcc4 (Digital), and Vcc9 (PLL2)
10.1.1.3
Vcc6 (PLL1 Charge Pump) and Vcc8 (PLL2 Charge Pump)
10.1.1.4
Vcc5 (CLKin and OSCout1), Vcc7 (OSCin and OSCout0)
10.1.2
LVPECL Outputs
10.1.3
Unused Clock Outputs
10.1.4
Unused Clock Inputs
10.1.5
LDO Bypass
10.2
Current Consumption and Power Dissipation Calculations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Device Support
12.1.1
Development Support
12.2
Documentation Support
12.2.1
Related Documentation
12.3
Related Links
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
封装选项
机械数据 (封装 | 引脚)
NKD|64
MPQS032B
散热焊盘机械数据 (封装 | 引脚)
NKD|64
QFND765
订购信息
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