Menu
Product
Email
PDF
Order now
THS3217 直流至 800MHz、差分转单端、DAC 输出放大器
ZHCSEP3B
February 2016 – February 2016
THS3217
PRODUCTION DATA.
CONTENTS
SEARCH
THS3217 直流至 800MHz、差分转单端、DAC 输出放大器
1
特性
2
应用
3
说明
4
修订历史记录
5
Device Comparison Table
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics: D2S
7.6
Electrical Characteristics: OPS
7.7
Electrical Characteristics: D2S + OPS
7.8
Electrical Characteristics: Midscale (DC) Reference Buffer
7.9
Typical Characteristics: D2S + OPS
7.10
Typical Characteristics: D2S Only
7.11
Typical Characteristics: OPS only
7.12
Typical Characteristics: Midscale (DC) Reference Buffer
7.13
Typical Characteristics: Switching Performance
7.14
Typical Characteristics: Miscellaneous Performance
8
Parameter Measurement Information
8.1
Overview
8.2
Frequency Response Measurement
8.3
Harmonic Distortion Measurement
8.4
Noise Measurement
8.5
Output Impedance Measurement
8.6
Step-Response Measurement
8.7
Feedthrough Measurement
8.8
Midscale Buffer ROUT Versus CLOAD Measurement
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Differential to Single-Ended Stage (D2S) With Fixed Gain of 2-V/V (Pins 2, 3, 6 and 14)
9.3.2
Midscale (DC) Reference Buffer (Pin 1 and Pin 15)
9.3.3
Output Power Stage (OPS) (Pins 4, 7, 9, 10, 11, and 12)
9.3.3.1
Output DC Offset and Drift for the OPS
9.3.3.2
OPS Harmonic Distortion (HD) Performance
9.3.3.3
Switch Feedthrough to the OPS
9.3.3.4
Driving Capacitive Loads
9.3.4
Digital Control Lines
9.4
Device Functional Modes
9.4.1
Full-Signal Path Mode
9.4.1.1
Internal Connection With Fixed Common-Mode Output Voltage
9.4.1.2
Internal Connection With Adjustable Common-Mode Output Voltage
9.4.1.3
External Connection
9.4.2
Dual-Output Mode
9.4.3
Differential I/O Voltage Mode
10
Application and Implementation
10.1
Application Information
10.1.1
Typical Applications
10.1.1.1
High-Frequency, High-Voltage, Dual-Output Line Driver for AWGs
10.1.1.1.1
Design Requirements
10.1.1.1.2
Detailed Design Procedure
10.1.1.1.3
Application Curves
10.1.1.2
High-Voltage Pulse-Generator
10.1.1.2.1
Design Requirements
10.1.1.2.2
Detailed Design Procedure
10.1.1.2.3
Application Curves
10.1.1.3
Single-Supply, AC-Coupled, Piezo Element Driver
10.1.1.3.1
Design Requirements
10.1.1.4
Output Common-Mode Control Using the Midscale Buffer as a Level Shifter
10.1.1.4.1
Design Requirements
10.1.1.5
Differential I/O Driver With independent Common-Mode Control
10.1.1.5.1
Design Requirements
11
Power Supply Recommendations
11.1
Thermal Considerations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
器件和文档支持
13.1
器件支持
13.1.1
开发支持
13.1.1.1
TINA-TI（免费软件下载）
13.2
文档支持
13.2.1
相关文档
13.3
社区资源
13.4
商标
13.5
静电放电警告
13.6
Glossary
14
机械、封装和可订购信息
重要声明
封装选项
机械数据 (封装 | 引脚)
RGV|16
MPQF121F
散热焊盘机械数据 (封装 | 引脚)
RGV|16
QFND107G
订购信息
zhcsep3b_oa
zhcsep3b_pm
search
No matches found.
Full reading width
Full reading width
Comfortable reading width
Expanded reading width
Card for each section
Card with all content
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP
|
米乐app下载官网（中国）|ios|Android/通用版APP最新版
|
米乐|米乐·M6（中国大陆）官方网站
|
千亿体育登陆地址
|
华体会体育（中国）HTH·官方网站
|
千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载
|
18新利网v1.2.5|中国官方网站
|
bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】
|
千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装
|