TLV62150x 采用 3x3 QFN 封装的 4V 至 17V 1A 降压转换器
- ZHCS759E February 2012 – September 2016 TLV62150 , TLV62150A
  
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TLV62150x 采用 3x3 QFN 封装的 4V 至 17V 1A 降压转换器

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

DCS-Control™拓扑技术
输入电压范围：4V 至 17V
输出电流高达 1A
0.9V 至 5V 可调节输出电压
引脚可选输出电压（标称值，+5%）
可编程软启动和跟踪
无缝节电模式转换
19µA 的静态电流（典型值）
可选运行频率
电源正常输出
100% 占空比模式
短路保护
过温保护
要了解改进的特性集，请见TPS62150
引脚至引脚兼容于 TLV62130
采用 3mm × 3mm 超薄四方扁平无引线 (VQFN)-16 封装

2 应用

标准 12V 导轨式电源
由单节或多节锂离子电池组成的负载点 (POL) 电源
电器、楼宇自动化
移动 PC、平板、调制解调器、摄像头
TV、机顶盒、音频

3 说明

TLV62150x 器件是一款简单易用的同步降压 DC-DC 转换器，针对高功率密度的应用进行了优化。该器件的开关频率典型值高达 2.5MHz，允许使用小型电感器，通过利用DCS-Control™ 拓扑提供快速瞬态响应并实现高输出电压精度。

此器件具有 4V 至 17V 宽运行输入电压范围，非常适用于由锂离子或其它电池以及 12V 中间电源轨供电的系统。其输出电压为 0.9V 至 5V，支持高达 1A 的持续输出电流（使用 100% 占空比模式）。

输出电压启动斜坡由软启动引脚控制，从而允许作为独立电源或者在跟踪配置下的运行。通过配置使能和开漏电源正常引脚也有可能实现电源排序。

在节能模式下，器件可根据输入电压 (VIN) 生成约 19μA 的静态电流。负载较小时可自动且无缝进入节能模式，同时该模式可保持整个负载范围内的高效率。在关断模式下，此器件会关闭且关断期间的流耗少于 2μA。

该器件采用 3mm × 3mm (RGT) 16 引脚超薄型四方扁平无引线 (VQFN) 封装。

器件信息⁽¹⁾

器件型号	封装	封装尺寸（标称值）
TLV62150	VQFN (16)	3.00mm x 3.00mm
TLV62150A	VQFN (16)	3.00mm x 3.00mm

要了解所有可用封装，请见数据表末尾的可订购米6体育平台手机版_好二三四附录。

空格

典型应用电路原理图		效率与输出电流间的关系


空白

4 修订历史记录

Changes from D Revision (August 2015) to E Revision

Added 引脚至引脚兼容能力至特性 Go
Added 项目至应用列表Go
Corrected temperatures in Thermal Information Go
Added Power Good Pin Logic Tables 1 and 2 Go
Added 接收文档更新通知 Go

Changes from C Revision (June 2015) to D Revision

Changed Power Good Threshold Voltage, Falling (%V_OUT) MAX spec from 93% to 94% Go

Changes from B Revision (June 2013) to C Revision

Added ESD 额定值表，特性描述部分，器件功能模式，应用和实现部分，电源相关建议部分，布局部分，器件和文档支持部分以及机械、封装和可订购信息部分Go

Changes from A Revision (February 2013) to B Revision

Added 新器件版本 TLV62150A 至数据表Go
Added text to Power Good section regarding the TLV62150A function.Go
Added additional option to the footnote for Pin-Selectable Output Voltage (DEF) section.Go
Added text to Frequency Selection (FSW) section regarding pin control.Go
Added text to Tracking Function section for clarification.Go
Changed schematic for Figure 38Go

Changes from * Revision (February 2012) to A Revision

Added text to Terminal Functions table to clarify Description for AGND, PGND, and Exposed Thermal Pad.Go
Added text to Power Save Mode Operation section for clarification.Go
Changed text in the Layout Considerations section for clarification.Go

5 Device Comparison Table

PART NUMBER	OUTPUT VOLTAGE	POWER GOOD LOGIC LEVEL (EN=Low)
TLV62150	Adjustable	High Impedance
TLV62150A	Adjustable	Low

6 Pin Configuration and Functions

RGT Package

16-Pin VQFN

Top View

space

Pin Functions

PIN⁽¹⁾		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
AGND	6	—	Analog Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.
AVIN	10	I	Supply voltage for control circuitry. Connect to same source as PVIN.
DEF	8	I	Output Voltage Scaling (Low = nominal, High = nominal + 5%)⁽³⁾
EN	13	I	Enable input (High = enabled, Low = disabled)⁽³⁾
FB	5	I	Voltage feedback. Connect resistive voltage divider to this pin.
FSW	7	I	Switching Frequency Select (Low ≈ 2.5 MHz, High ≈ 1.25 MHz⁽²⁾ for typical operation)⁽³⁾
SW	1,2,3	O	Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and output capacitor.
PG	4	O	Output power good (High = V_OUT ready, Low = V_OUT below nominal regulation) ; open drain (requires pull-up resistor)
PGND	15,16	—	Power ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.
PVIN	11,12	I	Supply voltage for power stage. Connect to same source as AVIN.
SS/TR	9	I	Soft-Start / Tracking Pin. An external capacitor connected to this pin sets the internal voltage reference rise time. It can be used for tracking and sequencing.
VOS	14	I	Output voltage sense pin and connection for the control loop circuitry.
Exposed Thermal Pad	—	—	Must be connected to AGND (pin 6), PGND (pin 15,16) and common ground plane. See the Layout Example. Must be soldered to achieve appropriate power dissipation and mechanical reliability.

(1) For more information about connecting pins, see Detailed Description and Application and Implementation sections.

(2) Connect FSW to VOUT or PG in this case.

(3) An internal pull-down resistor keeps logic level low, if pin is floating.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
Pin voltage ⁽²⁾	AVIN, PVIN	–0.3	20	V
	EN, SS/TR	–0.3	V_IN+0.3	V
	SW	–0.3	V_IN+0.3	V
	DEF, FSW, FB, PG, VOS	–0.3	7	V
Power Good sink current	PG		10	mA
Operating junction temperature	T_J	–40	125	°C
Storage temperature	T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to network ground terminal.

7.2 ESD Ratings

			VALUE		UNIT
V_ESD	Electrostatic discharge⁽¹⁾	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽²⁾	±2000		V
V_ESD	Electrostatic discharge⁽¹⁾	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽³⁾	±500		V

(1) ESD testing is performed according to the respective JESD22 JEDEC standard.

(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

	MIX	MAX	UNIT
Supply Voltage	4	17	V
Temperature Range, T_A	–40	85	°C
Operating junction temperature, T_J	–40	125	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		TLV62150	UNIT
		RGT [VQFN]
		16 PINS
R_θJA	Junction-to-ambient thermal resistance	45	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	53.6	°C/W
R_θJB	Junction-to-board thermal resistance	17.4	°C/W
ψ_JT	Junction-to-top characterization parameter	1.1	°C/W
ψ_JB	Junction-to-board characterization parameter	17.4	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	4.5	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over operating free-air temperature range (T_A = –40°C to 85°C), typical values at V_IN = 12 V and T_A = 25°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLY
V_IN	Input Voltage Range⁽¹⁾		4		17	V
I_Q	Operating Quiescent Current	EN=High, I_OUT=0 mA, device not switching		19	27	μA
I_SD	Shutdown Current ⁽²⁾	EN=Low		1.5	4	μA
V_UVLO	Undervoltage Lockout Threshold	Falling Input Voltage (PWM mode operation)	2.6	2.7	2.8	V
V_UVLO	Undervoltage Lockout Threshold	Hysteresis		200		mV
T_SD	Thermal Shutdown Temperature			160		°C
T_SD	Thermal Shutdown Hysteresis			20		°C
CONTROL (EN, DEF, FSW, SS/TR, PG)
V_H	High Level Input Threshold Voltage (EN, DEF, FSW)		0.9			V
V_L	Low Level Input Threshold Voltage (EN, DEF, FSW)				0.3	V
I_LKG	Input Leakage Current (EN, DEF, FSW)	EN=V_IN or GND; DEF, FSW=V_OUT or GND		0.01	1	μA
V_{TH_PG}	Power Good Threshold Voltage	Rising (%V_OUT)	92%	95%	98%
V_{TH_PG}	Power Good Threshold Voltage	Falling (%V_OUT)	87%	90%	94%
V_{OL_PG}	Power Good Output Low	I_PG=-2 mA		0.07	0.3	V
I_{LKG_PG}	Input Leakage Current (PG)	V_PG=1.8 V		1	400	nA
I_SS/TR	SS/TR Pin Source Current		2.3	2.5	2.7	μA
POWER SWITCH
R_DS(ON)	High-Side MOSFET ON-Resistance	V_IN≥6 V		90		mΩ
R_DS(ON)	Low-Side MOSFET ON-Resistance	V_IN≥6 V		40		mΩ
I_LIMF	High-Side MOSFET Forward Current Limit⁽³⁾	V_IN=12 V, T_A=25°C	1.4	1.7		A
OUTPUT
I_{LKG_FB}	Input Leakage Current (FB)	V_FB=0.8 V		1	100	nA
V_OUT	Output Voltage Range	V_IN ≥ V_OUT	0.9		5	V
	DEF (Output Voltage Programming)	DEF=0 (GND)		V_OUT
	DEF (Output Voltage Programming)	DEF=1 (V_OUT)		V_OUT+5%
	Initial Output Voltage Accuracy⁽⁴⁾	PWM mode operation, V_IN ≥ V_OUT +1 V	780	800	820	mV
	Load Regulation⁽⁵⁾	V_IN=12 V, V_OUT=3.3 V, PWM mode operation		0.05		%/A
	Line Regulation⁽⁵⁾	4 V ≤ V_IN ≤ 17 V, V_OUT=3.3 V, I_OUT= 1 A, PWM mode operation		0.02		%/V

(1) The device is still functional down to Under Voltage Lockout (see parameter VUVLO).

(2) Current into AVIN+PVIN pin.

(3) This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current Limit and Short Circuit Protection).

(4) This is the accuracy provided by the device itself (line and load regulation effects are not included).

(5) Line and load regulation depend on external component selection and layout (see Figure 20 and Figure 21).

7.6 Typical Characteristics

Figure 1. Quiescent Current

Figure 3. High-Side Switch Resistance

Figure 2. Shutdown Current

Figure 4. Low-Side Switch Resistance