ZHCSJX9
June 2019
TPS652170
PRODUCTION DATA.
1
特性
2
应用
3
说明
Device Images
简化应用示意图
4
修订历史记录
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
I2C Timing Requirements
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Wake-Up and Power-Up Sequencing
7.3.1.1
Power-Up Sequencing
7.3.1.2
Power-Down Sequencing
7.3.1.3
Special Strobes (STROBE 14 and 15)
7.3.2
Power Good
7.3.2.1
LDO1, LDO2 Power-Good (LDO_PGOOD)
7.3.2.2
Primary Power-Good (PGOOD)
7.3.2.3
Load Switch PGOOD
7.3.3
Push-Button Monitor (PB_IN)
7.3.4
nWAKEUP Pin (nWAKEUP)
7.3.5
Power Enable Pin (PWR_EN)
7.3.6
Reset Pin (nRESET)
7.3.7
Interrupt Pin (nINT)
7.3.8
Analog Multiplexer
7.3.9
Battery Charger and Power Path
7.3.9.1
Shorted or Absent Battery (VBAT < 1.5 V)
7.3.9.2
Dead Battery (1.5 V < VBAT < VUVLO)
7.3.9.3
Good Battery (VBAT > VUVLO)
7.3.9.4
AC and USB Input Discharge
7.3.10
Battery Charging
7.3.11
Precharge
7.3.12
Charge Termination
7.3.13
Battery Detection and Recharge
7.3.14
Safety Timer
7.3.14.1
Dynamic Timer Function
7.3.14.2
Timer Fault
7.3.15
Battery-Pack Temperature Monitoring
7.3.16
DC/DC Converters
7.3.16.1
Operation
7.3.16.2
Output Voltage Setting
7.3.16.3
Power-Save Mode and Pulse-Frequency Modulation (PFM)
7.3.16.4
Dynamic Voltage Positioning
7.3.16.5
100% Duty-Cycle Low-Dropout Operation
7.3.16.6
Short-Circuit Protection
7.3.16.7
Soft Start
7.3.17
Standby LDO Regulators (LDO1, LDO2)
7.3.18
Load Switches or LDO Regulators (LS1 or LDO3, LS2 or LDO4)
7.3.19
White LED Driver
7.4
Device Functional Modes
7.4.1
PMIC States
7.4.1.1
OFF State
7.4.1.2
ACTIVE State
7.4.1.3
SLEEP State
7.4.1.4
RESET State
7.5
Programming
7.5.1
I2C Bus Operation
7.5.2
Password Protection
7.5.2.1
Level1 Protection
7.5.2.2
Level2 Protection
7.5.3
Resetting of Registers to Default Values
7.6
Register Maps
7.6.1
Register Address Map
7.6.1.1
Programming Power-Up Default Values
7.6.2
Chip ID Register (CHIPID) (Address = 0x00) [reset = 0x02]
Table 2.
CHIPID Register Field Descriptions
7.6.3
Power Path Control Register (PPATH) (Address = 0x01) [reset = 0x3D]
Table 3.
PPATH Register Field Descriptions
7.6.4
Interrupt Register (INT) (Address = 0x02) [reset = 0x80]
Table 4.
INT Register Field Descriptions
7.6.5
Charger Configuration Register 0 (CHGCONFIG0) (Address = 0x03) [reset = 0x00]
Table 5.
CHGCONFIG0 Register Field Descriptions
7.6.6
Charger Configuration Register 1 (CHGCONFIG1) (Address = 0x04) [reset = 0xB1]
Table 6.
CHGCONFIG1 Register Field Descriptions
7.6.7
Charger Configuration Register 2 (CHGCONFIG2) (Address = 0x05) [reset = 0x80]
Table 7.
CHGCONFIG2 Register Field Descriptions
7.6.8
Charger Configuration Register 3 (CHGCONFIG3) (Address = 0x06) [reset = 0xB2]
Table 8.
CHGCONFIG3 Register Field Descriptions
7.6.9
WLED Control Register 1 (WLEDCTRL1) (Address = 0x07) [reset = 0xB1]
Table 9.
WLEDCTRL1 Register Field Descriptions
7.6.10
WLED Control Register 2 (WLEDCTRL2) (Address = 0x08) [reset = 0x00]
Table 10.
WLEDCTRL2 Register Field Descriptions
7.6.11
MUX Control Register (MUXCTRL) (Address = 0x09) [reset = 0x00]
Table 11.
MUXCTRL Register Field Descriptions
7.6.12
Status Register (STATUS) (Address = 0x0A) [reset = 0x00]
Table 12.
STATUS Register Field Descriptions
7.6.13
Password Register (PASSWORD) (Address = 0x0B) [reset = 0x00]
Table 13.
Password Register (PASSWORD) Field Descriptions
7.6.14
Power Good Register (PGOOD) (Address = 0x0C) [reset = 0x00]
Table 14.
PGOOD Register Field Descriptions
7.6.15
Power-Good Control Register (DEFPG) (Address = 0x0D) [reset = 0x0C]
Table 15.
DEFPG Register Field Descriptions
7.6.16
DCDC1 Control Register (DEFDCDC1) (Address = 0x0E) [reset = 0x18]
Table 16.
DEFDCDC1 Register Field Descriptions
7.6.17
DCDC2 Control Register (DEFDCDC2) (Address = 0x0F) [reset = 0x08]
Table 17.
DEFDCDC2 Register Field Descriptions
7.6.18
DCDC3 Control Register (DEFDCDC3) (Address = 0x10) [reset = 0x08]
Table 18.
DEFDCDC3 Register Field Descriptions
7.6.19
Slew-Rate Control Register (DEFSLEW) (Address = 0x11) [reset = 0x06]
Table 19.
DEFSLEW Register Field Descriptions
7.6.20
LDO1 Control Register (DEFLDO1) (Address = 0x12) [reset = 0x09]
Table 20.
DEFLDO1 Register Field Descriptions
7.6.21
LDO2 Control Register (DEFLDO2) (Address = 0x13) [reset = 0x38]
Table 21.
DEFLDO2 Register Field Descriptions
7.6.22
Load Switch1 or LDO3 Control Register (DEFLS1) (Address = 0x14) [reset = 0x26]
Table 22.
DEFLS1 Register Field Descriptions
7.6.23
Load Switch2 or LDO4 Control Register (DEFLS2) (Address = 0x15) [reset = 0x3F]
Table 23.
DEFLS2 Register Field Descriptions
7.6.24
Enable Register (ENABLE) (Address = 0x16) [reset = 0x00]
Table 24.
ENABLE Register Field Descriptions
7.6.25
UVLO Control Register (DEFUVLO) (Address = 0x18) [reset = 0x00]
Table 25.
DEFUVLO Register Field Descriptions
7.6.26
Sequencer Register 1 (SEQ1) (Address = 0x19) [reset = 0x00]
Table 26.
SEQ1 Register Field Descriptions
7.6.27
Sequencer Register 2 (SEQ2) (Address = 0x1A) [reset = 0x00]
Table 27.
SEQ2 Register Field Descriptions
7.6.28
Sequencer Register 3 (SEQ3) (Address = 0x1B) [reset = 0x00]
Table 28.
SEQ3 Register Field Descriptions
7.6.29
Sequencer Register 4 (SEQ4) (Address = 0x1C) [reset = 0x40]
Table 29.
SEQ4 Register Field Descriptions
7.6.30
Sequencer Register 5 (SEQ5) (Address = 0x1D) [reset = 0x20]
Table 30.
SEQ5 Register Field Descriptions
7.6.31
Sequencer Register 6 (SEQ6) (Address = 0x1E) [reset = 0x00]
Table 31.
SEQ6 Register Field Descriptions
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Output Filter Design (Inductor and Output Capacitor)
8.2.2.1.1
Inductor Selection for Buck Converters
8.2.2.1.2
Output Capacitor Selection
8.2.2.1.3
Input Capacitor Selection
8.2.2.2
5-V Operation Without a Battery
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
器件和文档支持
11.1
器件支持
11.1.1
第三方米6体育平台手机版_好二三四免责声明
11.2
文档支持
11.2.1
相关文档
11.3
接收文档更新通知
11.4
社区资源
11.5
商标
11.6
静电放电警告
11.7
Glossary
12
机械、封装和可订购信息
封装选项
请参考 PDF 数据表获取器件具体的封装图。
机械数据 (封装 | 引脚)
RSL|48
散热焊盘机械数据 (封装 | 引脚)
RSL|48
QFND160K
订购信息
zhcsjx9_oa
1
特性
充电器和电源路径
电源路径上具有 2A 输出电流
线性充电器;700mA 最大充电电流
可耐受 20V USB 和交流输入
热调节,安全计时器
温度检测输入
降压转换器(DCDC1、DCDC2、DCDC3)
三个具有集成开关 FET 的降压转换器
2.25MHz 固定频率运行
轻负载电流状态下进入节能模式
PWM 模式下输出电压精度为 ±2%
100% 占空比,可实现最低压降
每个转换器的静态电流典型值为 15µA
禁用时支持无源对地放电
LDO 稳压器(LDO1、LDO2)
两个可调 LDO
LDO2 可配置为跟踪 DCDC3
15µA 静态电流(典型值)
负载开关(LDO3、LDO4)
两个可配置为 LDO 的独立负载开关
WLED 驱动器
内部生成的 PWM 可支持调光控制
38V 开路 LED 保护
支持两个 LED 灯串(每串多达 10 个 LED,每个 LED 的电流为 25mA)
内部低侧灌电流
保护
欠压锁定和电池故障比较器
常开按钮监视器
硬件复位引脚
受密码保护的 I
2
C 寄存器
接口
I
2
C 接口(地址 0x24)
受密码保护的 I
2
C 寄存器
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