SLASF07
September 2023
DAC43901-Q1
,
DAC43902-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics: Comparator Mode
6.6
Electrical Characteristics: General
6.7
Timing Requirements: I2C Standard Mode
6.8
Timing Requirements: I2C Fast Mode
6.9
Timing Requirements: I2C Fast-Mode Plus
6.10
Timing Requirements: SPI Write Operation
6.11
Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
6.12
Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
6.13
Timing Requirements: PWM Output
6.14
Timing Diagrams
6.15
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Smart Digital-to-Analog Converter (DAC) Architecture
7.3.2
Threshold DAC
7.3.2.1
Voltage Reference and DAC Transfer Function
7.3.2.2
Power-Supply as Reference
7.3.2.3
Internal Reference
7.3.2.4
External Reference
7.3.3
Programming Interface
7.3.4
Nonvolatile Memory (NVM)
7.3.4.1
NVM Cyclic Redundancy Check (CRC)
7.3.4.1.1
NVM-CRC-FAIL-USER Bit
7.3.4.1.2
NVM-CRC-FAIL-INT Bit
7.3.5
Power-On Reset (POR)
7.3.6
External Reset
7.3.7
Register-Map Lock
7.4
Device Functional Modes
7.4.1
Comparator Mode
7.4.2
PWM Fade-In Fade-Out Mode
7.4.3
Sequential Turn-Indicator Animation Mode
7.5
Programming
7.5.1
SPI Programming Mode
7.5.2
I2C Programming Mode
7.5.2.1
F/S Mode Protocol
7.5.2.2
I2C Update Sequence
7.5.2.2.1
Address Byte
7.5.2.2.2
Command Byte
7.5.2.3
I2C Read Sequence
7.6
Register Maps
7.6.1
NOP Register (address = 00h) [reset = 0000h]
7.6.2
DAC-x-VOUT-CMP-CONFIG Register (address = 15h, 03h)
7.6.3
COMMON-CONFIG Register (address = 1Fh)
7.6.4
COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
7.6.5
COMMON-PWM-TRIG Register (address = 21h) [reset = 0000h]
7.6.6
GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
7.6.7
INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
7.6.8
STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
7.6.9
SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
7.6.10
SRAM-DATA Register (address = 2Ch) [reset = 0000h]
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
Sequential Turn Indicator
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.3
Application Curve
8.2.2
Logarithmic Fade-In Fade-Out
8.2.2.1
Design Requirements
8.2.2.2
Detailed Design Procedure
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Receiving Notification of Documentation Updates
9.2
Support Resources
9.3
Trademarks
9.4
Electrostatic Discharge Caution
9.5
Glossary
10
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RTE|16
MPQF149D
Thermal pad, mechanical data (Package|Pins)
RTE|16
QFND525B
Orderable Information
slasf07_oa
slasf07_pm
Data Sheet
DAC4390x-Q1 Automotive Smart DACs for Logarithmic Fade-In Fade-Out and Sequential Turn Animation With I
2
C, SPI, GPIO, and PWM Interfaces
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