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DLPC4420 DLP Display Controller
DLPS222A
December 2021 – February 2023
DLPC4420
PRODUCTION DATA
CONTENTS
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DLPC4420 DLP Display Controller
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
System Oscillators Timing Requirements
6.7
Test and Reset Timing Requirements
6.8
JTAG Interface: I/O Boundary Scan Application Timing Requirements
6.9
Port 1 Input Pixel Timing Requirements
6.10
Port 3 Input Pixel Interface (via GPIO) Timing Requirements
6.11
DMD LVDS Interface Timing Requirements
6.12
Synchronous Serial Port (SSP) Interface Timing Requirements
6.13
Programmable Output Clocks Switching Characteristics
6.14
Synchronous Serial Port Interface (SSP) Switching Characteristics
6.15
JTAG Interface: I/O Boundary Scan Application Switching Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
System Reset Operation
7.3.1.1
Power-Up Reset Operation
7.3.1.2
System Reset Operation
7.3.2
Spread Spectrum Clock Generator Support
7.3.3
GPIO Interface
7.3.4
Source Input Blanking
7.3.5
Video Graphics Processing Delay
7.3.6
Program Memory Flash/SRAM Interface
7.3.7
Calibration and Debug Support
7.3.8
Board Level Test Support
7.4
Device Functional Modes
7.4.1
Standby Mode
7.4.2
Active Mode
7.4.2.1
Normal Configuration
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.1.1
Recommended MOSC Crystal Oscillator Configuration
8.2.2
Detailed Design Procedure
9
Power Supply Recommendations
9.1
System Power Regulations
9.2
System Power-Up Sequence
9.3
Power-On Sense (POSENSE) Support
9.4
System Environment and Defaults
9.4.1
DLPC4420 System Power-Up and Reset Default Conditions
9.4.2
1.1V System Power
9.4.3
1.8V System Power
9.4.4
3.3V System Power
9.4.5
Power Good (PWRGOOD) Support
9.4.6
5V Tolerant Support
10
Layout
10.1
Layout Guidelines
10.1.1
PCB Layout Guidelines for Internal DLPC4420 Power
10.1.2
PCB Layout Guidelines for Auto-Lock Performance
10.1.3
DMD Interface Considerations
10.1.4
Layout Example
10.1.5
Thermal Considerations
11
Device and Documentation Support
11.1
Third-Party Products Disclaimer
11.2
Device Support
11.2.1
Video Timing Parameter Definitions
11.2.2
Device Nomenclature
11.2.3
Device Markings
11.2.3.1
Device Marking
11.3
Documentation Support
11.3.1
Related Documentation
11.4
Receiving Notification of Documentation Updates
11.5
Support Resources
11.6
Trademarks
11.7
Electrostatic Discharge Caution
11.8
Glossary
12
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
ZPC|516
MPBGAJ0
Thermal pad, mechanical data (Package|Pins)
Orderable Information
dlps222a_oa
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