SLVSFY8B
February 2020 – August 2021
DRV8210
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Device Comparison
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Typical Characteristics DSG Package
7.7
Typical Characteristics DRL Package
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
External Components
8.3.2
Control Modes
8.3.2.1
PWM Control Mode (DSG: MODE = 0 and DRL)
8.3.2.2
PH/EN Control Mode (DSG: MODE = 1)
8.3.2.3
Half-Bridge Control Mode (DSG: MODE = Hi-Z)
8.3.3
Protection Circuits
8.3.3.1
Supply Undervoltage Lockout (UVLO)
8.3.3.2
OUTx Overcurrent Protection (OCP)
8.3.3.3
Thermal Shutdown (TSD)
8.3.4
Pin Diagrams
8.3.4.1
Logic-Level Inputs
8.3.4.2
Tri-Level Input
8.4
Device Functional Modes
8.4.1
Active Mode
8.4.2
Low-Power Sleep Mode
8.4.3
Fault Mode
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Full-Bridge Driving
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.2.1
Supply Voltage
9.2.1.2.2
Control Interface
9.2.1.2.3
Low-Power Operation
9.2.1.3
Application Curves
9.2.2
Half-Bridge Driving
9.2.2.1
Design Requirements
9.2.2.2
Detailed Design Procedure
9.2.2.2.1
Supply Voltage
9.2.2.2.2
Control Interface
9.2.2.2.3
Low-Power Operation
9.2.2.3
Application Curves
9.2.3
Dual-Coil Relay Driving
9.2.3.1
Design Requirements
9.2.3.2
Detailed Design Procedure
9.2.3.2.1
Supply Voltage
9.2.3.2.2
Control Interface
9.2.3.2.3
Low-Power Operation
9.2.3.3
Application Curves
9.2.4
Current Sense
9.2.4.1
Design Requirements
9.2.4.2
Detailed Design Procedure
9.2.4.2.1
Shunt Resistor Sizing
9.2.4.2.2
RC Filter
9.3
Current Capability and Thermal Performance
9.3.1
Power Dissipation and Output Current Capability
9.3.2
Thermal Performance
9.3.2.1
Steady-State Thermal Performance
9.3.2.2
Transient Thermal Performance
10
Power Supply Recommendations
10.1
Bulk Capacitance
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
Support Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DSG|8
MPDS308C
DRL|6
MPDS159H
Thermal pad, mechanical data (Package|Pins)
DSG|8
QFND141I
Orderable Information
slvsfy8b_oa
slvsfy8b_pm
1
Features
N-channel H-bridge motor driver
MOSFET on-resistance: HS + LS 1 Ω
Drives one bidirectional brushed DC motor
Two unidirectional brushed DC motors
One single- or dual-coil latching relay
Push-pull and bistable solenoids
Other resistive, inductive, or LED loads
1.65-V to 11-V operating supply voltage range
High output current capability:
Full-bridge: 1.76-A peak
Half-bridge: 1.76-A peak per output
Parallel half-bridge: 3.52-A peak
Multiple interfaces for flexibility and reduced GPIO
Standard PWM Interface (IN1/IN2)
Supports 1.8-V, 3.3-V, and 5-V logic inputs
Ultra low-power sleep mode
<84.5 nA @ V
VM
= 5 V, V
VCC
= 3.3 V, T
J
= 25°C
Timed autosleep mode to reduce GPIO
Protection features
Undervoltage lockout (UVLO)
Overcurrent protection (OCP)
Thermal shutdown (TSD)
Family of devices. See
Device Comparison
for details.
DRV8210
: 1.65-11 V, 1 Ω, multiple interfaces
DRV8210P
: Sleep pin, PWM interface
DRV8212
: 1.65-11 V, 280 mΩ, multiple interfaces
DRV8212P
: Sleep pin, PWM interface
DRV8220
: 4.5-18 V, 1 Ω, multiple interfaces
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