SCES579J JUNE 2004 – September 2017 SN74AUP1G17
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics
- 6.6 Switching Characteristics: CL = 5 pF
- 6.7 Switching Characteristics: CL = 10 pF
- 6.8 Switching Characteristics: CL = 15 pF
- 6.9 Switching Characteristics: CL = 30 pF
- 6.10 Operating Characteristics
- 6.11 Typical Characteristics
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
1 Features
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
(A114-B, Class II) - 1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model
- Available in the Texas Instruments NanoStar™ Package
- Low Static-Power Consumption
(ICC = 0.9 µA Maximum) - Low Dynamic-Power Consumption
(Cpd = 4.4 pF Typical at 3.3 V) - Low Input Capacitance (Ci = 1.5 pF Typical)
- Low Noise – Overshoot and Undershoot
<10% of VCC - Ioff Supports Partial-Power-Down Mode Operation
- Includes Schmitt-Trigger Inputs
- Wide Operating VCC Range of 0.8 V to 3.6 V
- Optimized for 3.3-V Operation
- 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- tpd = 5.1 ns Maximum at 3.3 V
- Suitable for Point-to-Point Applications
2 Applications
- Grid Infrastructure
- PC & Notebooks
- Tablets
- Factory Automation & Control
- Gaming
- Server
3 Description
The AUP family of devices is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life. This product also maintains excellent signal integrity (see AUP – The Lowest-Power Family and Excellent Signal Integrity).
This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition and better switching-noise immunity at the input.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| SN74AUP1G17DBV | SOT-23 (5) | 1.60 mm × 2.90 mm |
| SN74AUP1G17DCK | SC70 (5) | 1.25 mm × 2.00 mm |
| SN74AUP1G17DRL | SOT-5X3 (5) | 1.60 mm × 1.20 mm |
| SN74AUP1G17DRY | SON (6) | 1.00 mm × 1.45 mm |
| SN74AUP1G17DSF | SON (6) | 1.00 mm × 1.00 mm |
| SN74AUP1G17YFP | DSBGA (4) | 0.76 mm × 0.76 mm |
| SN74AUP1G17YZP | DSBGA (5) | 0.89 mm × 1.39 mm |
| SN74AUP1G17DPW | X2SON (5) | 0.80 mm × 0.80 mm |
- For all available packages, see the orderable addendum at the end of the data sheet.
Logic Diagram (Positive Logic)
(DBV, DCK, DPW, DRL, DRT, DRY, and YZP Packages)
Logic Diagram (Positive Logic)
(YFP Package)
