SLVSCV0B August   2015  – September 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 GND
      2. 8.3.2 VIN
      3. 8.3.3 dV/dT
      4. 8.3.4 BFET
      5. 8.3.5 EN/UVLO
      6. 8.3.6 ILIM
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Simple 3.7-A eFuse Protection for Set Top Boxes
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Step by Step Design Procedure
          2. 9.2.1.2.2 Programming the Current-Limit Threshold: RILIM Selection
          3. 9.2.1.2.3 Undervoltage Lockout Set Point
          4. 9.2.1.2.4 Setting Output Voltage Ramp Time (TdVdT)
            1. 9.2.1.2.4.1 Case 1: Start-Up without Load: Only Output Capacitance COUT Draws Current During Start-Up
            2. 9.2.1.2.4.2 Case 2: Start-Up with Load: Output Capacitance COUT and Load Draws Current During Start-Up
          5. 9.2.1.2.5 Support Component Selection—CVIN
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Inrush and Reverse Current Protection for Hold-Up Capacitor Application (for example, SSD)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Programming the Current-Limit Threshold: RILIM Selection
          2. 9.2.2.2.2 Undervoltage Lockout Set Point
          3. 9.2.2.2.3 Setting Output Voltage Ramp Time (TdVdT)
          4. 9.2.2.2.4 Support Component Selection - CVIN
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Controlled Power Down using TPS25923x
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
    2. 10.2 Output Short-Circuit Measurements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • 5-V eFuse, VABSMAX = 20 V
  • Integrated 28-mΩ Pass MOSFET
  • Fixed 6.1-V Over Voltage Clamp
  • 1-A to 5-A Adjustable ILIMIT
  • ±8% ILIMIT Accuracy at 3.7A
  • Reverse Current Blocking Support
  • Programmable OUT Slew Rate, UVLO
  • Built-in Thermal Shutdown
  • UL 2367 Recognized – File No. E339631*
    • *RILIM ≤ 130 kΩ (5 A maximum)
  • Safe During Single Point Failure Test (UL60950)
  • Small Foot Print – 10L (3 mm x 3 mm) VSON

2 Applications

  • Adapter Powered Devices
  • HDD and SSD Drives
  • Set Top Boxes
  • Servers / AUX Supplies
  • Fan Control
  • PCI/PCIe Cards

3 Description

The TPS25923x family of eFuses is a highly integrated circuit protection and power management solution in a tiny package. The devices use few external components and provide multiple protection modes. They are a robust defense against overloads, shorts circuits, voltage surges, excessive inrush current, and reverse current.

Current limit level can be set with a single external resistor. Over voltage events are limited by internal clamping circuits to a safe fixed maximum, with no external components required. Applications with particular voltage ramp requirements can set dV/dT with a single capacitor to ensure proper output ramp rates.

Many systems, such as SSDs, must not allow holdup capacitance energy to dump back through the FET body diode onto a drooping or shorted input bus. The BFET pin is for such systems. An external NFET can be connected “Back to Back (B2B)” with the TPS25923x output and the gate driven by BFET to prevent current flow from load to source (see Figure 43).

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPS259230 VSON (10) 3.00 mm × 3.00 mm
TPS259231
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Application Schematic

TPS259230 TPS259231 top_page_slvscv0.gif

Transient: Output Short Circuit

TPS259230 TPS259231 FP_Fig_26_37_slvscv0.png
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