SWRS045F
January 2006 – November 2018
CC1021
PRODUCTION DATA.
1
Device Overview
1.1
Features
1.2
Applications
1.3
Description
1.4
Functional Block Diagram
2
Revision History
3
Terminal Configuration and Functions
3.1
Pin Diagram
3.2
Pin Configuration
4
Specifications
4.1
Absolute Maximum Ratings
4.2
ESD Ratings
4.3
Recommended Operating Conditions
4.4
RF Transmit
4.5
RF Receive
4.6
RSSI / Carrier Sense
4.7
Intermediate Frequency (IF)
4.8
Crystal Oscillator
4.9
Frequency Synthesizer
4.10
Digital Inputs / Outputs
4.11
Current Consumption
4.12
Thermal Resistance Characteristics for VQFNP Package
5
Detailed Description
5.1
Overview
5.2
Functional Block Diagram
5.3
Configuration Overview
5.3.1
Configuration Software
5.4
Microcontroller Interface
5.4.1
Configuration Interface
5.4.2
Signal Interface
5.4.3
PLL Lock Signal
5.5
4-wire Serial Configuration Interface
5.6
Signal Interface
5.6.1
Synchronous NRZ Mode
5.6.2
Transparent Asynchronous UART Mode
5.6.3
Synchronous Manchester Encoded Mode
5.6.3.1
Manchester Encoding and Decoding
5.7
Data Rate Programming
5.8
Frequency Programming
5.8.1
Dithering
5.9
Receiver
5.9.1
IF Frequency
5.9.2
Receiver Channel Filter Bandwidth
5.9.3
Demodulator, Bit Synchronizer and Data Decision
5.9.4
Receiver Sensitivity versus Data Rate and Frequency Separation
5.9.5
RSSI
5.9.6
Image Rejection Calibration
5.9.7
Blocking and Selectivity
5.9.8
Linear IF Chain and AGC Settings
5.9.9
AGC Settling
5.9.10
Preamble Length and Sync Word
5.9.11
Carrier Sense
5.9.12
Automatic Power-Up Sequencing
5.9.13
Automatic Frequency Control
5.9.14
Digital FM
5.10
Transmitter
5.10.1
FSK Modulation Formats
5.10.2
Output Power Programming
5.10.3
TX Data Latency
5.10.4
Reducing Spurious Emission and Modulation Bandwidth
5.11
Input and Output Matching and Filtering
5.12
Frequency Synthesizer
5.12.1
VCO, Charge Pump, and PLL Loop Filter
5.12.2
VCO and PLL Self-Calibration
5.12.3
PLL Turn-on Time versus Loop Filter Bandwidth
5.12.4
PLL Lock Time versus Loop Filter Bandwidth
5.13
VCO and LNA Current Control
5.14
Power Management
5.15
On-Off Keying (OOK)
5.16
Crystal Oscillator
5.17
Built-in Test Pattern Generator
5.18
Interrupt on Pin DCLK
5.18.1
Interrupt Upon PLL Lock
5.18.2
Interrupt Upon Received Signal Carrier Sense
5.19
PA_EN and LNA_EN Digital Output Pins
5.19.1
Interfacing an External LNA or PA
5.19.2
General-Purpose Output Control Pins
5.19.3
PA_EN and LNA_EN Pin Drive
5.20
System Considerations and Guidelines
5.20.1
SRD Regulations
5.20.2
Narrowband Systems
5.20.3
Low Cost Systems
5.20.4
Battery Operated Systems
5.20.5
High Reliability Systems
5.20.6
Frequency Hopping Spread Spectrum Systems (FHSS)
5.21
Antenna Considerations
5.22
Configuration Registers
5.22.1
Memory
6
Applications, Implementation, and Layout
6.1
Application Information
6.1.1
Typical Application
6.2
Design Requirements
6.2.1
Input / Output Matching
6.2.2
Bias Resistor
6.2.3
PLL Loop Filter
6.2.4
Crystal
6.2.5
Additional Filtering
6.2.6
Power Supply Decoupling and Filtering
6.3
PCB Layout Guidelines
7
Device and Documentation Support
7.1
Device Support
7.1.1
Device Nomenclature
7.2
Documentation Support
7.2.1
Community Resources
7.3
Trademarks
7.4
Electrostatic Discharge Caution
7.5
Export Control Notice
7.6
Glossary
8
Mechanical Packaging and Orderable Information
8.1
Packaging Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RSS|32
MPQF200B
サーマルパッド・メカニカル・データ
RSS|32
QFND548
発注情報
swrs045f_oa
1
Device Overview
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