1 Features

• Distributes One Differential Clock Input Pair LVPECL to 10 Differential LVPECL
• Fully Compatible With LVECL and LVPECL
• Supports a Wide Supply Voltage Range from 2.375 V to 3.8 V
• Selectable Clock Input Through CLK_SEL
• Low-Output Skew (Typical 15 ps) for Clock-Distribution Applications
  • Additive Jitter Less Than 1 ps
  • Propagation Delay Less Than 350 ps
  • Open Input Default State
  • LVDS, CML, SSTL Input Compatible
• V_BB Reference Voltage Output for Single-Ended Clocking
• Available in a 32-Pin LQFP and QFN Package
• Frequency Range From DC to 3.5 GHz
• Pin-to-Pin Compatible With MC100 Series EP111, ES6111, LVEP111, PTN1111

2 Applications

• Designed for Driving 50-Ω Transmission Lines
• High Performance Clock Distribution

3 Description

The CDCLVP111 clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111 can accept two clock sources into an input multiplexer. The CDCLVP111 is specifically designed for driving 50-Ω transmission lines. When an output pin is not used, leaving it open is recommended to reduce power consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically terminated to 50 Ω.

The V_BB reference voltage output is used if single-ended input operation is required. In this case, the V_BB pin should be connected to CLK0 and bypassed to GND through a 10-nF capacitor.

However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.

The CDCLVP111 device is characterized for operation from –40°C to 85°C.

1. For all available packages, see the orderable addendum at the end of the data sheet.

Functional Block Diagram