SNOSAY8F September   2007  – April 2015 DP83640

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Pin Configuration and Functions
    1. 3.1  Pin Layout
    2. 3.2  Package Pin Assignments
    3. 3.3  Serial Management Interface (SMI)
    4. 3.4  MAC Data Interface
    5. 3.5  Clock Interface
    6. 3.6  LED Interface
    7. 3.7  IEEE 1588 Event/Trigger/Clock Interface
    8. 3.8  JTAG Interface
    9. 3.9  Reset and Power Down
    10. 3.10 Strap Options
    11. 3.11 10 Mb/s and 100 Mb/s PMD Interface
    12. 3.12 Power Supply Pins
  4. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 DC Specifications
    6. 4.6 AC Timing Requirements
  5. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Media Configuration
      2. 5.3.2 Auto-Negotiation
        1. 5.3.2.1 Auto-Negotiation Pin Control
        2. 5.3.2.2 Auto-Negotiation Register Control
        3. 5.3.2.3 Auto-Negotiation Parallel Detection
        4. 5.3.2.4 Auto-Negotiation Restart
        5. 5.3.2.5 Enabling Auto-Negotiation Through Software
        6. 5.3.2.6 Auto-Negotiation Complete Time
      3. 5.3.3 Auto-MDIX
      4. 5.3.4 LED Interface
        1. 5.3.4.1 LEDs
        2. 5.3.4.2 LED Direct Control
      5. 5.3.5 Internal Loopback
      6. 5.3.6 Power Down/Interrupt
        1. 5.3.6.1 Power Down Control Mode
        2. 5.3.6.2 Interrupt Mechanisms
      7. 5.3.7 Energy Detect Mode
      8. 5.3.8 Link Diagnostic Capabilities
        1. 5.3.8.1 Linked Cable Status
          1. 5.3.8.1.1 Polarity Reversal
          2. 5.3.8.1.2 Cable Swap Indication
          3. 5.3.8.1.3 100-Mb Cable Length Estimation
          4. 5.3.8.1.4 Frequency Offset Relative to Link Partner
          5. 5.3.8.1.5 Cable Signal Quality Estimation
        2. 5.3.8.2 Link Quality Monitor
          1. 5.3.8.2.1 Link Quality Monitor Control and Status
          2. 5.3.8.2.2 Checking Current Parameter Values
          3. 5.3.8.2.3 Threshold Control
        3. 5.3.8.3 TDR Cable Diagnostics
        4. 5.3.8.4 TDR Pulse Generator
        5. 5.3.8.5 TDR Pulse Monitor
        6. 5.3.8.6 TDR Control Interface
        7. 5.3.8.7 TDR Results
      9. 5.3.9 BIST
    4. 5.4 Device Functional Modes
      1. 5.4.1  MAC Interface
      2. 5.4.2  MII Interface
        1. 5.4.2.1 Nibble-Wide MII Data Interface
        2. 5.4.2.2 Collision Detect
        3. 5.4.2.3 Carrier Sense
      3. 5.4.3  Reduced MII Interface
        1. 5.4.3.1 RMII Master Mode
        2. 5.4.3.2 RMII Slave Mode
      4. 5.4.4  Single Clock MII Mode
      5. 5.4.5  IEEE 802.3 MII Serial Management Interface
        1. 5.4.5.1 Serial Management Register Access
        2. 5.4.5.2 Serial Management Access Protocol
        3. 5.4.5.3 Serial Management Preamble Suppression
      6. 5.4.6  PHY Control Frames
      7. 5.4.7  PHY Status Frames
      8. 5.4.8  PHY Address
        1. 5.4.8.1 MII Isolate Mode
        2. 5.4.8.2 Broadcast Mode
      9. 5.4.9  Half Duplex vs. Full Duplex
      10. 5.4.10 Reset Operation
        1. 5.4.10.1 Hardware Reset
        2. 5.4.10.2 Full Software Reset
        3. 5.4.10.3 Soft Reset
        4. 5.4.10.4 PTP Reset
    5. 5.5 Programming
      1. 5.5.1 Architecture
        1. 5.5.1.1 100BASE-TX Transmitter
          1. 5.5.1.1.1 Code-Group Encoding and Injection
          2. 5.5.1.1.2 Scrambler
          3. 5.5.1.1.3 NRZ to NRZI Encoder
          4. 5.5.1.1.4 Binary to MLT-3 Convertor
        2. 5.5.1.2 100BASE-TX Receiver
          1. 5.5.1.2.1  Analog Front End
          2. 5.5.1.2.2  Digital Signal Processor
            1. 5.5.1.2.2.1 Base Line Wander Compensation
            2. 5.5.1.2.2.2 Digital Adaptive Equalization and Gain Control
          3. 5.5.1.2.3  Signal Detect
          4. 5.5.1.2.4  MLT-3 to Binary Decoder
          5. 5.5.1.2.5  Clock Recovery Module
          6. 5.5.1.2.6  NRZI to NRZ Decoder
          7. 5.5.1.2.7  Serial-to-Parallel
          8. 5.5.1.2.8  Descrambler
          9. 5.5.1.2.9  Code-Group Alignment
          10. 5.5.1.2.10 4B/5B Decoder
          11. 5.5.1.2.11 100BASE-TX Link Integrity Monitor
          12. 5.5.1.2.12 Bad SSD Detection
        3. 5.5.1.3 100BASE-FX Operation
          1. 5.5.1.3.1 100BASE-FX Transmit
          2. 5.5.1.3.2 100BASE-FX Receive
          3. 5.5.1.3.3 Far-End Fault
        4. 5.5.1.4 10BASE-T Transceiver Module
          1. 5.5.1.4.1  Operational Modes
          2. 5.5.1.4.2  Smart Squelch
          3. 5.5.1.4.3  Collision Detection and SQE
          4. 5.5.1.4.4  Carrier Sense
          5. 5.5.1.4.5  Normal Link Pulse Detection/Generation
          6. 5.5.1.4.6  Jabber Function
          7. 5.5.1.4.7  Automatic Link Polarity Detection and Correction
          8. 5.5.1.4.8  Transmit and Receive Filtering
          9. 5.5.1.4.9  Transmitter
          10. 5.5.1.4.10 Receiver
    6. 5.6 Memory
      1. 5.6.1 Register Block
        1. 5.6.1.1 Register Definition
          1. 5.6.1.1.1  Basic Mode Control Register (BMCR)
          2. 5.6.1.1.2  Basic Mode Status Register (BMSR)
          3. 5.6.1.1.3  PHY Identifier Register #1 (PHYIDR1)
          4. 5.6.1.1.4  PHY Identifier Register #2 (PHYIDR2)
          5. 5.6.1.1.5  Auto-Negotiation Advertisement Register (ANAR)
          6. 5.6.1.1.6  Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
          7. 5.6.1.1.7  Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page)
          8. 5.6.1.1.8  Auto-Negotiate Expansion Register (ANER)
          9. 5.6.1.1.9  Auto-Negotiation Next Page Transmit Register (ANNPTR)
          10. 5.6.1.1.10 PHY Status Register (PHYSTS)
          11. 5.6.1.1.11 MII Interrupt Control Register (MICR)
          12. 5.6.1.1.12 MII Interrupt Status and Event Control Register (MISR)
          13. 5.6.1.1.13 Page Select Register (PAGESEL)
        2. 5.6.1.2 Extended Registers - Page 0
          1. 5.6.1.2.1  False Carrier Sense Counter Register (FCSCR)
          2. 5.6.1.2.2  Receiver Error Counter Register (RECR)
          3. 5.6.1.2.3  100 Mb/s PCS Configuration and Status Register (PCSR)
          4. 5.6.1.2.4  RMII and Bypass Register (RBR)
          5. 5.6.1.2.5  LED Direct Control Register (LEDCR)
          6. 5.6.1.2.6  PHY Control Register (PHYCR)
          7. 5.6.1.2.7  10Base-T Status/Control Register (10BTSCR)
          8. 5.6.1.2.8  CD Test and BIST Extensions Register (CDCTRL1)
          9. 5.6.1.2.9  PHY Control Register 2 (PHYCR2)
          10. 5.6.1.2.10 Energy Detect Control (EDCR)
          11. 5.6.1.2.11 PHY Control Frames Configuration Register (PCFCR)
        3. 5.6.1.3 Test Registers - Page 1
          1. 5.6.1.3.1 Signal Detect Configuration (SD_CNFG), Page 1
        4. 5.6.1.4 Link Diagnostics Registers - Page 2
          1. 5.6.1.4.1  100 Mb Length Detect Register (LEN100_DET), Page 2
          2. 5.6.1.4.2  100 Mb Frequency Offset Indication Register (FREQ100), Page 2
          3. 5.6.1.4.3  TDR Control Register (TDR_CTRL), Page 2
          4. 5.6.1.4.4  TDR Window Register (TDR_WIN), Page 2
          5. 5.6.1.4.5  TDR Peak Register (TDR_PEAK), Page 2
          6. 5.6.1.4.6  TDR Threshold Register (TDR_THR), Page 2
          7. 5.6.1.4.7  Variance Control Register (VAR_CTRL), Page 2
          8. 5.6.1.4.8  Variance Data Register (VAR_DATA), Page 2
          9. 5.6.1.4.9  Link Quality Monitor Register (LQMR), Page 2
          10. 5.6.1.4.10 Link Quality Data Register (LQDR), Page 2
          11. 5.6.1.4.11 Link Quality Monitor Register 2 (LQMR2), Page 2
        5. 5.6.1.5 PTP 1588 Base Registers - Page 4
          1. 5.6.1.5.1  PTP Control Register (PTP_CTL), Page 4
          2. 5.6.1.5.2  PTP Time Data Register (PTP_TDR), Page 4
          3. 5.6.1.5.3  PTP Status Register (PTP_STS), Page 4
          4. 5.6.1.5.4  PTP Trigger Status Register (PTP_TSTS), Page 4
          5. 5.6.1.5.5  PTP Rate Low Register (PTP_RATEL), Page 4
          6. 5.6.1.5.6  PTP Rate High Register (PTP_RATEH), Page 4
          7. 5.6.1.5.7  PTP Read Checksum (PTP_RDCKSUM), Page 4
          8. 5.6.1.5.8  PTP Write Checksum (PTP_WRCKSUM), Page 4
          9. 5.6.1.5.9  PTP Transmit Timestamp Register (PTP_TXTS), Page 4
          10. 5.6.1.5.10 PTP Receive Timestamp Register (PTP_RXTS), Page 4
          11. 5.6.1.5.11 PTP Event Status Register (PTP_ESTS), Page 4
          12. 5.6.1.5.12 PTP Event Data Register (PTP_EDATA), Page 4
        6. 5.6.1.6 PTP 1588 Configuration Registers - Page 5
          1. 5.6.1.6.1  PTP Trigger Configuration Register (PTP_TRIG), Page 5
          2. 5.6.1.6.2  PTP Event Configuration Register (PTP_EVNT), Page 5
          3. 5.6.1.6.3  PTP Transmit Configuration Register 0 (PTP_TXCFG0), Page 5
          4. 5.6.1.6.4  PTP Transmit Configuration Register 1 (PTP_TXCFG1), Page 5
          5. 5.6.1.6.5  PHY Status Frame Configuration Register 0 (PSF_CFG0), Page 5
          6. 5.6.1.6.6  PTP Receive Configuration Register 0 (PTP_RXCFG0), Page 5,
          7. 5.6.1.6.7  PTP Receive Configuration Register 1 (PTP_RXCFG1), Page 5
          8. 5.6.1.6.8  PTP Receive Configuration Register 2 (PTP_RXCFG2), Page 5
          9. 5.6.1.6.9  PTP Receive Configuration Register 3 (PTP_RXCFG3), Page 5
          10. 5.6.1.6.10 PTP Receive Configuration Register 4 (PTP_RXCFG4), Page 5
          11. 5.6.1.6.11 PTP Temporary Rate Duration Low Register (PTP_TRDL), Page 5
          12. 5.6.1.6.12 PTP Temporary Rate Duration High Register (PTP_TRDH), Page 5
        7. 5.6.1.7 PTP 1588 Configuration Registers - Page 6
          1. 5.6.1.7.1  PTP Clock Output Control Register (PTP_COC), Page 6
          2. 5.6.1.7.2  PHY Status Frame Configuration Register 1 (PSF_CFG1), Page 6
          3. 5.6.1.7.3  PHY Status Frame Configuration Register 2 (PSF_CFG2), Page 6
          4. 5.6.1.7.4  PHY Status Frame Configuration Register 3 (PSF_CFG3), Page 6
          5. 5.6.1.7.5  PHY Status Frame Configuration Register 4 (PSF_CFG4), Page 6
          6. 5.6.1.7.6  PTP SFD Configuration Register (PTP_SFDCFG), Page 6
          7. 5.6.1.7.7  PTP Interrupt Control Register (PTP_INTCTL), Page 6
          8. 5.6.1.7.8  PTP Clock Source Register (PTP_CLKSRC), Page 6
          9. 5.6.1.7.9  PTP Ethernet Type Register (PTP_ETR), Page 6
          10. 5.6.1.7.10 PTP Offset Register (PTP_OFF), Page 6
          11. 5.6.1.7.11 PTP GPIO Monitor Register (PTP_GPIOMON), Page 6
          12. 5.6.1.7.12 PTP Receive Hash Register (PTP_RXHASH), Page 6
  6. 6Application, Implementation, and Layout
    1. 6.1 Application Information
      1. 6.1.1 Key IEEE 1588 Features
        1. 6.1.1.1 IEEE 1588 Synchronized Clock
          1. 6.1.1.1.1 IEEE 1588 Clock Output
          2. 6.1.1.1.2 IEEE 1588 Clock Input
        2. 6.1.1.2 Packet Timestamps
          1. 6.1.1.2.1 IEEE 1588 Transmit Packet Parser and Timestamp
            1. 6.1.1.2.1.1 One-Step Operation
          2. 6.1.1.2.2 IEEE 1588 Receive Packet Parser and Timestamp
            1. 6.1.1.2.2.1 Receive Timestamp Insertion
          3. 6.1.1.2.3 NTP Packet Timestamp
        3. 6.1.1.3 Event Triggering and Timestamping
          1. 6.1.1.3.1 IEEE 1588 Event Triggering
          2. 6.1.1.3.2 IEEE 1588 Event Timestamping
        4. 6.1.1.4 PTP Interrupts
        5. 6.1.1.5 GPIO
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
        1. 6.2.1.1 TPI Network Circuit
        2. 6.2.1.2 Fiber Network Circuit
        3. 6.2.1.3 ESD Protection
        4. 6.2.1.4 Clock In (X1) Recommendations
          1. 6.2.1.4.1 Oscillator
          2. 6.2.1.4.2 Crystal
        5. 6.2.1.5 Magnetics
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 MAC Interface (MII/RMII)
          1. 6.2.2.1.1 Termination Requirement
          2. 6.2.2.1.2 Recommended Maximum Trace Length
        2. 6.2.2.2 Calculating Impedance
          1. 6.2.2.2.1 Microstrip Impedance - Single-Ended
          2. 6.2.2.2.2 Stripline Impedance - Single-Ended
          3. 6.2.2.2.3 Microstrip Impedance - Differential
          4. 6.2.2.2.4 Stripline Impedance - Differential
      3. 6.2.3 Application Curves
    3. 6.3 Layout
      1. 6.3.1 Layout Guidelines
        1. 6.3.1.1 PCB Layout Considerations
        2. 6.3.1.2 PCB Layer Stacking
      2. 6.3.2 Layout Example
    4. 6.4 Power Supply Recommendations
  7. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Trademarks
    3. 7.3 Electrostatic Discharge Caution
    4. 7.4 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

1 Device Overview

1.1 Features

  • IEEE 1588 V1 and V2 Supported
  • UDP/IPv4, UDP/IPv6, and Layer2 Ethernet Packets Supported
  • IEEE 1588 Clock Synchronization
  • Timestamp Resolution of 8 ns
  • Allows Sub 10-ns Synchronization to Master Reference
  • 12 IEEE 1588 GPIOs for Trigger or Capture
  • Deterministic, Low Transmit and Receive Latency
  • Selectable Frequency Synchronized Clock Output
  • Dynamic Link Quality Monitoring
  • TDR Based Cable Diagnostic and Cable Length Detection
  • 10/100 Mb/s Packet BIST (Built-in Self Test)
  • Error-Free Operation up to 150 Meters CAT5 Cable
  • ESD Protection - 8 kV Human Body Model
  • 2.5-V and 3.3-V I/Os and MAC Interface
  • Auto-MDIX for 10/100 Mbps
  • RMII Rev. 1.2 and MII MAC Interface
  • 25-MHz MDC and MDIO Serial Management Interface
  • IEEE 802.3 100BASE-FX Fiber Interface
  • IEEE 1149.1 JTAG
  • Programmable LED Support for Link, 10/100 Mb/s Mode, Duplex, Activity, and Collision Detect
  • Optional 100BASE-TX Fast Link-loss Detection
  • Industrial Temperature Range
  • 48-pin LQFP Package (7 mm × 7 mm)

1.2 Applications

  • Factory Automation
    • Ethernet/IP
    • CIP Sync
  • Test and Measurement
    • LXI Standard
  • Telecom
    • Basestation
  • Real Time Networking

1.3 Description

The DP83640 Precision PHYTER™ device delivers the highest level of precision clock synchronization for real time industrial connectivity based on the IEEE 1588 standard. The DP83640 has deterministic, low latency and allows choice of microcontroller with no hardware customization required. The integrated 1588 functionality allows system designers the flexibility and precision of a close to the wire timestamp. The three key 1588 features supported by the device are:

  • Packet time stamps for clock synchronization
  • Integrated IEEE 1588 synchronized clock generation
  • Synchronized event triggering and time stamping through GPIO

DP83640 offers innovative diagnostic features unique to Texas Instruments, including dynamic monitoring of link quality during standard operation for fault prediction. These advanced features allow the system designer to implement a fault prediction mechanism to detect and warn of deteriorating and changing link conditions. This single port fast Ethernet transceiver can support both copper and fiber media.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DP83640 LQFP (48) 7.00 mm × 7.00 mm
(1) For more information, see Section 8, Mechanical Packaging and Orderable Information.

1.4 Functional Block Diagram

DP83640 30011218.gif
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