改訂履歴

Changes from * Revision (March 2017) to A Revision

• Changed ドキュメント全体で TI Design をリファレンス・デザインにGo
• Changed ドキュメント全体で TMS320F28379 を TMS320F280025C にGo
• Changed controlSUITE を Digital Power SDK にGo
• Deleted 「...および入力低電圧 / 過電圧」をGo
• Changed Delfine to Third GenerationGo
• Changed Four independent 16-bit... to Two independent 12-bit...Go
• Added The duty can be reduced all the way to 0% if necessary, putting the PWM module into a burst mode.Go
• Changed CMPSS2 to CMPSS4Go
• Deleted ...for the transformer high voltage winding current for each phase...Go
• Changed CMPSS5 to CMPSS2Go
• Added Output overvoltage protection is implemented using on-chip analog comparator 3. Go
• Added ...or voltageGo
• Deleted Output overvoltage protection is implemented in the software inside the state machine task A1. Whenever an output overvoltage is detected, a one-shot trip action is initiated on ePWM1, ePWM2, ePWM4, and ePWM5.Go
• Deleted The software also sets the system fault LEF under these fault conditions. Input undervoltage and overvoltage protection are implemented in the software inside the slower state machine task C2. These conditions disable LLC operation and all PWMs are held in low state. LLC operation and the PWMs are re-enabled once the input comes back within programmed limits and stays good for a programmable time interval.Go
• Changed ADC-C2 to CMPSS3Go
• Added Vout, Heavily filtered output voltage feedback, ADC-A8Go
• Changed ADC-C4/CMPSS6 to CMPSS2Go
• Changed ADC-B0 to ADC-COGo
• Changed ADC-A2/CMPSS1 /to CMPSS1Go
• Changed ADC-A4/CMPSS2to CMPSS4Go
• Changed ADC-C0 to ADC-C8Go
• Deleted ...consists of two components, both...Go
• Deleted The Fast Update ISR portion is triggered by the master swiitching PWM (phase one HB driver PWM) which is only executed when there is a change in frequency or when a sysem comment requires a fast update.Go
• Added A PID controller is included as an option. Only the PI coefficients can be designed with Compensation Designer, but a user defined set of coefficients is defined in llc_user_settings.h and can be used to define a manually tuned PID controller. The PID Controller Tuning Guide provided in the documentation for the Digital Control Library provides guidance that can be used for this process.Go
• Changed HV2PHILLLC-Main.c to llc_main.cGo
• Added Driver code for the TMS320F280025C device is in llc_hal.c / llc_hal.h files. The llc.c / llc.h files have all the...Go
• Deleted This file is the brains behind the application and contains all time crtical...Go
• Added time-criticalGo
• Added ..., as well as the other code specific to the powerstage including phase shedding, current balancing, and SR enable / disable. User configurable settings for the project are included in the llc_user_settings.h file. The llc_settings.h file is automatically generated by the powerSUITE GUI and if developing with powerSUITE enabled, any modifications to llc_settings.h will be overwritten when the project is built. Go
• Deleted Table 3. Software Library ModulesGo
• Deleted Although a two-pole,two-zero controller is used, the controller could very well be a PI , PID, a three-pole three-zero, or any other controller that can be suitably implemented for this application.Go
• Changed Incremental Builds to Incremental LabsGo
• Changed ...two incremental builds... to four incremental labs...Go
• Changed ...shows the incremental build options. To select a particular built option in main.cfg... to ...shows the lab options. To select a particular lab, select the corresponding project option in main.syscfgGo
• Changed build to labGo
• Changed Table 3. Incremental Build Options to Incremental Lab OptionsGo
• Changed INCR_BUILD to LLC_LabGo
• Added LLC_LAB = 3, LLC-LAB = 4 rows to the tableGo
• Changed Procedure for Running the Incremental Builds to Procedure for Running the Incremental LabsGo
• Changed version 6.1 to version 9.3Go
• Changed Build to LabGo
• Added ...shows the software block diagram for lab 1.Go
• Changed imageGo
• Changed ...main.cfg to ...lc_user_settings.hGo
• Changed ...Variable Period to LLC_periodReg_debug_puGo
• Changed ...ISR funtion Update Regs to LLC_run/SR1().Go
• Deleted ...by using the variable Period_Set.Go
• Changed main.cfg to llc_user_settings_hGo
• Changed CMPSSs 1, 2, and 5 to CMPSSs 1, 2, 3, and 4Go
• Changed ...can be set using the GUI_Lpri1tripSet, Gui_lpri2tripSetvariables to are defined in the llc_settings.h file: LLC_IPRI1_TRIP_AMPS, LLC_IPRI2_TRIP_AMPS, LLC_ISEC_TRIP_AMPS, LLC_VSEC_TRIP_VOLTS. These define statements set the trip configurations for phase 1 primary current, phase 2 primary current, secondary (output) current, and secondary voltage respectively. The values can be adjusted in the powerSUITE GUI.Go
• Changed ...Period_Set_pu to LLC_periodSet_puGo
• Changed The DPL_ISR_wFRA_ISR is triggered by the master PWM module(PWM1). This ISR is where the control code and digital power library modules are executed. to The control ISR is triggered by a spare PWM module at a rate of 50 KHz, but the project supports increasing the control frequency up to 100 KHz. Go
• Changed CCS version 6.1 to CCS version 9.3Go
• Changed controlSuite, and CCS GUI composer to Digital Power SDK, and CCS SysConfig utilityGo
• Changed 18-pin connectors J3 and J4 to 120-pin connector J3.Go
• Changed version 6.1 to version 9.3Go
• Changed A project contains all the files and build options required to develop an executable output file (.out), which can be run on the MCR hardware. On the menu bar click Projet > Import CCS Project. Below the root directory, navigate to and select ..controlSUITE development kits directory. Make sure that below the Projects tab, HVsPHILLLC is selected... to On the menu bar click Project >Import CCS Project. Below the root directory, navigate to and select ..\C2000Ware_DigitalPower_SDK_X_XX_XX_XX\solutions\tidm_1001\f28002x\llc directory. Make sure that below the Projects tab, 2PH_IL_LLC_F28002x is selected.Go
• Changed HV2PHILLLC project should now appear in the CCS Project Explorer window. This project will invoke all the necessary tools (compiler, assembler, and linker) to builg the project. A project contains all the files and build options required to develop an executable output file (.out), which can be run on the MCU hardware to 2PH_IL_LLC_F28002x project should now appear in the CCS Project Explorer window. This project will invoke all the necessary tools (compiler, assembler, and linker) to build the project. A project contains all the files and build options required to develop an executable output file (.out), which can be run on the MCU hardware.Go
• Changed Open main.cfg file by double clicking on the... to If not already open, double click the main.sysconfig fi...Go
• Changed main.cfg to main.syscfgGo
• Deleted Note that the default software does not allow phase shedding in this build regardless of this selection in the main.cfg.Go
• Changed Build One: main.cfg to Lab One: main.syscfgGo
• Changed build to labGo
• Deleted ...build oneGo
• Changed AddWatchWindowVars.js to setupdebugenv_lab1.jsGo
• Changed Build One to Lab OneGo
• Changed data in entireTable 4Go
• Changed Period_Set to LLC_periodSet_puGo
• Changed 250_kHz to 350-kHzGo
• Deleted (resonent frequenty)Go
• Added Verify that all of the sensed values are updating in the expressions window: LLC_vPri_Volts, LLC_iPri_PH1_Amps, LLC_iPri_PH2_Amps, LLC_iSec_Amps.Go
• Deleted Period_SetGo
• Changed 0.0 to 0.57 and 0.95 to 1.00Go
• Deleted Period_Set has been restricted to a maximum value of 0.95 in this build.Go
• Added The LLC_dutySet_PH1_debug_pu, and LLC_dutySet_PH2_debug_pu variables are initialized to 0.99, but they may be set to values between 0.05 and 0.99. An oscilloscope may be used to observe the changing duty cycle for the switch waveforms. Go
• Deleted ...shows the Expressions Window that corresponds to the operatoin of the system when Period_Set is 0.8. Period_Set - 0.8Built One: Expressions Window With...Go
• Changed main.cfg to main.syscfgGo
• Changed Build One to Lab OneGo
• Changed Build One to Lab OneGo
• Changed build to labGo
• Changed Build Two to Lab TwoGo
• Changed CNTL_2P2Z to CL_runDF22_C1 Go
• Added The option for a PID controller module (DCL_runPID_C1) is also provided and can be selected from the powerSUITE GUI. Go
• Changed ADC_Vout to LLC_vSec_pu; CNTL_2P2Z to controller; Vout_ref_win to LLC_VSecSet_puGo
• Changed The controller output Period LLC_periodSet_pu is used to update PWM registers similar to build one. The output voltage command can be adjusted from the Expressions Window using the variable Gui_VSet to The controller output LLC_periodSet_pu is used by the driver to update PWM registers similar to lab one. The output voltage command can be adjusted from the Expressions Window using the variable LLC_vSecRef_debug_VoltsGo
• Changed main.cfg to llc_user_settings_hGo
• Changed protection (for the TIDM-1001 board these are CMPSSs 1, 2, and 5). The reference trip level for the comparators can be set using the GUI_lpri1tripSet, Sui_Ipri2tripSet, and Gui_IouttripSet variables. to and overvoltage protection (for the TIDM-1001 board these are CMPSSs 1, 2, and 5). The reference trip level for the comparators can be set using the powerSUITE GUI, which updates the LLC_IPRI1_TRIP_AMPS, LLC_IPRI2_TRIP_AMPS, LLC_ISEC_TRIP_AMPS, LLC_VSEC_TRIP_VOLTS defines in the LLC_settings.h file.Go
• Changed main.cfg to llc_user_setings_hGo
• Added or voltageGo
• Changed The DPL_ISR_wFRA ISR is triggered by the masters PWM module (PWM1). This ISR is where the control code and digital power library modules are executed. to The ISR is triggered by a spare PWM module (PWM3). This ISR is where the control code is executed.Go
• Changed build to labGo
• Deleted item 1Go
• Added Follow the steps inthe software setup section for lab 1 to open the powerSUITE_GUI.Go
• Changed select Closed Voltage Loop to in the powerSUITE GUI select to Closed Loop. Go
• Changed ...main.cfg file (here COMP3). to ...main.syscfg file (COMP1).Go
• Added Compensation Designer GUIGo
• Changed COMP3 to COMP1Go
• Added When any changes are made in Compensation Designer the "Save COMP" button will write the updated coefficients into the project.' and , and PID compensators. The Compensation Designer GUI supports tuning only the PI coefficients of the PID controller, so if derivative action is desired the PID controller will have to be tuned manually. Go
• Changed COMP3 to COMP1; main.cfg to main.syscfgGo
• Added Follow the steps in...for lab one procedureGo
• Deleted Turn ON the 12 V auxiliary supply. If another lab option was built previously, right click on the project name, and click on Clean Project. Click Project > Build All button, and watch the tools run in the build window. Click on the Debug button ( ) or click Run > Debug. The build one code should compile and load build. Notice the CCS Debug icon in the upper right-corner, which indicates the Debug Perspective view. The program should be stopped at the start of main ( ).Go
• Changed AddWatchWindowVars.js to setupdebugenv_lab2.jsGo
• Changed Built Two to Lab TwoGo
• Added Table 5 title: Description of Expressions Window EntriesGo
• Deleted (default is 0) at the top of the HVwPHILLLC Main c file #define DEMO_MODE 1 When operating in stand-alone (DEMO mode) the converter operation should begin at this point, and the output voltage should ramp up to approximately 12V. DEMO mode can be selected by programming.Go
• Changed start_flag to LLC_startFlagGo
• Deleted or the FaultFig is Set,Go
• Deleted shows a watch window that corresponds to the operation of the system with 12 V at the output, an input voltge of 390 V, and a load of approximately 20 A Build Two: Expressions Window with Iout - 20AGo
• Changed Built Two to Lab TwoGo
• Changed in the graph window as shown in... to as observed on an oscilloscope...Go
• Added These input voltage and output load will also affect the power stage dynamics, and the values reported by the SFRA GUI. Go
• Added subtitle: Lab Three: Closed-Loop Control With Current Balancing and SFRA Go
• Added Subtitle: Lab Four: Closed-Loop Control With Current Balancing, Phase Shedding, Synchronous Rectification Threshold, and SFRA Go
• Added Overview subsectionGo
• Added The software block diagram is shown in Figure 34.Go
• Added Figure 34; Subsections: Procedure, hardware Setup, Software Setup, Build and Load the Project, Debug Environment WindowsGo
• Added Subtitle: Using Realtime EmulationGo
• Added Follow the steps in for lab one procedure. Go
• Added Subtitle: Run the CodeGo
• Added Refer to steps 1-6 in...Go
• Added additional list items.Go
• Changed controlSuite > English to Software > C2000Ware_DigitalPower_SDKGo
• Changed LLC 2PH INTERLEAVEC-DC to DC-DCGo
• Changed F28379D to F280025C optionGo
• Changed main.cfg to main.syscfgGo