SCES881
February 2020
SN74AXCH2T45
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Logic Diagram (Positive Logic)
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics, VCCA = 0.7 ± 0.05 V
6.7
Switching Characteristics, VCCA = 0.8 ± 0.045 V
6.8
Switching Characteristics, VCCA = 0.9 ± 0.04 V
6.9
Switching Characteristics, VCCA = 1.2 ± 0.1 V
6.10
Switching Characteristics, VCCA = 1.5 ± 0.1 V
6.11
Switching Characteristics, VCCA = 1.8 ± 0.15 V
6.12
Switching Characteristics, VCCA = 2.5 ± 0.2 V
6.13
Switching Characteristics, VCCA = 3.3 ± 0.3 V
6.14
Operating Characteristics: TA = 25°C
7
Parameter Measurement Information
7.1
Load Circuit and Voltage Waveforms
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Standard CMOS Inputs
8.3.2
Balanced High-Drive CMOS Push-Pull Outputs
8.3.3
Partial Power Down (Ioff)
8.3.4
VCC Isolation
8.3.5
Over-voltage Tolerant Inputs
8.3.6
Glitch-free Power Supply Sequencing
8.3.7
Negative Clamping Diodes
8.3.8
Fully Configurable Dual-Rail Design
8.3.9
Supports High-Speed Translation
8.4
Bus-Hold Data Inputs
8.5
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.1.1
Enable Times
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curve
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
Support Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DCU|8
MPDS050E
DTM|8
MPSS118A
サーマルパッド・メカニカル・データ
発注情報
sces881_oa
sces881_pm
1
Features
Fully configurable dual-rail design allows each port to operate with a power supply range from 0.65 V to 3.6 V
Operating temperature from –40°C to +125°C
Glitch-free power supply sequencing
Up to 380 Mbps support when translating from 1.8 V to 3.3 V
V
CC
isolation feature
If either V
CC
input is below 100 mV, all I/O outputs are disabled and become high impedance
I
off
supports partial-power-down mode operation
Compatible with AVC family level shifters
Latch-up performance exceeds 100 mA per JESD 78, Class II
ESD protection exceeds JESD 22
8000-V human-body model (HBM)
1000-V charged-device model (CDM)
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