JAJSKF6C
November 2020 – December 2021
TPS2661
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements
7.7
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Overload Protection and Fast-Trip
8.3.2
Reverse Current Blocking for Unipolar Current Inputs TPS26610, TPS26611 and TPS26612 (4–20 mA, 0–20 mA)
8.3.3
OUTPUT and INPUT Cutoff During Overvoltage, Undervoltage Due to Miswiring
8.3.3.1
Output Overvoltage With TPS2661x Devices
8.3.3.2
Output or Input Undervoltage With TPS26610, TPS26611 and TPS26612
8.3.3.3
Output Undervoltage With TPS26613 and TPS26614
8.3.4
External Power Supply (±Vs)
8.3.5
Loop Testing Without ±Vs Supply (Loop Power Mode in TPS26610, TPS26613 Only)
8.3.5.1
Supply Sensing With VSNS for Loop Power Mode With TPS26610 and TPS26613
8.3.6
Enable Control With TPS26611, TPS26612, and TPS26614
8.3.7
Signal Good Indicator (SGOOD)
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application: Analog Input Protection for Current Inputs with TPS26610
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure for Current Inputs with TPS26610
9.2.2.1
Selecting ±Vs Supplies for TPS26610
9.2.2.2
Selecting RBurden
9.2.2.3
Selecting MODE Configuration for TPS26610
9.2.3
Application Performance Plots for Current Inputs with TPS26610
9.3
Typical Application: Analog Input Protection for Multiplexed Current and Voltage Inputs with TPS26611
9.3.1
Design Requirements
9.3.2
Detailed Design Procedure for Analog Input Protection for Multiplexed Current and Voltage Inputs with TPS26611
9.3.2.1
Selecting ±Vs Supplies for TPS26611
9.3.2.2
Selecting MODE Configuration for TPS26611
9.3.2.3
Selecting Bias Resistors R1, R2 for Setting Common Mode Voltage for Voltage Inputs
9.3.3
Application Performance Plots for V/I Inputs with TPS26611
9.4
System Examples
9.4.1
Power Supply Protection of 2-Wire Transmitter with TPS26612
9.4.2
Protection of 3-Wire Transmitters and Analog Output Modules With TPS26611, TPS26612
9.4.3
UART IO Protection With TPS26611, TPS26612
9.4.4
Higher Loop Impedance With TPS26613 and TPS26614
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Receiving Notification of Documentation Updates
12.2
サポート・リソース
12.3
Trademarks
12.4
Electrostatic Discharge Caution
12.5
Glossary
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DDF|8
MPDS569D
サーマルパッド・メカニカル・データ
発注情報
jajskf6c_oa
jajskf6c_pm
1
特長
±50V の動作電圧、±55V の絶対最大定格
内蔵の固定バイポーラ 32mA 電流制限機能
スタートアップ時に電流制限の倍増が可能
代表的なディスクリート保護回路と比較して 50% のスペース節減
低いオン抵抗:7.5Ω (標準値)
低い I
Q
(< 100nA) - 外部電源から電力を供給している際にループから流れ出る電流
IN と OUT の誤配線状態に対して保護
信号ラインのサージ (IEC61000-4-5) 中の保護 (外部 TVS 併用)
判定基準 A EFT (IEC61000-4-4) 耐性 (外部 TVS 併用)
電源なしのループ・テストをサポート (TPS26610 のみ)
HART 準拠
イネーブル制御
SGOOD
によるシステムの健全性の監視
サーマル・シャットダウン
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