SLVSCJ5C
December 2015 – September 2024
TPS7H3301-SP
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
VTT/VO Sink and Source Regulator
7.3.2
Reference Input (VDDQSNS)
7.3.3
Reference Output (VTTREF)
7.3.4
EN Control (EN)
7.3.5
Power-Good Function (PGOOD)
7.3.6
VTT Current Protection
7.3.7
VIN UVLO Protection
7.3.8
Thermal Shutdown
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
VDD/VIN Capacitor
8.2.2.2
VLDO Input Capacitor
8.2.2.3
VTT Output Capacitor
8.2.2.4
VTTSNS Connection
8.2.2.5
Low VIN Applications
8.2.2.6
S3 and Pseudo-S5 Support
8.2.2.7
Tracking Startup and Shutdown
8.2.2.8
Output Tolerance Consideration for VTT DIMM or Module Applications
8.2.2.9
LDO Design Guidelines
8.2.3
Application Curve
Power Supply Recommendations
9
Layout
9.1
Layout Guidelines
9.2
Layout Example
9.3
Thermal Considerations
10
Device and Documentation Support
10.1
Device Support
10.1.1
Third-Party Products Disclaimer
10.2
Documentation Support
10.2.1
Related Documentation
10.3
Receiving Notification of Documentation Updates
10.4
Support Resources
10.5
Trademarks
10.6
Electrostatic Discharge Caution
10.7
Glossary
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
HKR|16
MCDF012C
サーマルパッド・メカニカル・データ
発注情報
slvscj5c_oa
slvscj5c_pm
Data Sheet
TPS7H3301-SP Sink and Source Radiation-Hardened 3-A DDR Termination Regulator
With Built-In VTTREF Buffer
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