SBOA272C December   2020  – January 2021 LMC7101 , OPA170

 

  1.   1

Design Goals

Input 1 Input 2 Output Freq. Supply
Vi1Min Vi1Max Vi2Min Vi2Max VoMin VoMax f Vcc Vee
–2.5V 2.5V –250mV 250mV –4.9V 4.9V 10kHz 5V –5V

Design Description

This design sums (adds) and inverts two input signals, Vi1 and Vi2. The input signals typically come from low-impedance sources because the input impedance of this circuit is determined by the input resistors, R1 and R2. The common-mode voltage of an inverting amplifier is equal to the voltage connected to the non-inverting node, which is ground in this design.

GUID-01B4A617-5C38-46CB-B179-AC00175BB9E2-low.gif

Design Notes

  1. Use the op amp in a linear operating region. Linear output swing is usually specified under the AOL test conditions. The common-mode voltage in this circuit does not vary with input voltage.
  2. The input impedance is determined by the input resistors. Make sure these values are large when compared to the output impedance of the source.
  3. Using high-value resistors can degrade the phase margin of the circuit and introduce additional noise in the circuit.
  4. Avoid placing capacitive loads directly on the output of the amplifier to minimize stability issues.
  5. Small-signal bandwidth is determined by the noise gain (or non-inverting gain) and op amp gain-bandwidth product (GBP). Additional filtering can be accomplished by adding a capacitor in parallel to R3. Adding a capacitor in parallel with R3 will also improve stability of the circuit if high-value resistors are used.
  6. Large signal performance may be limited by slew rate. Therefore, check the maximum output swing versus frequency plot in the data sheet to minimize slew-induced distortion.
  7. For more information on op amp linear operating region, stability, slew-induced distortion, capacitive load drive, driving ADCs, and bandwidth please see the Design References section.

Design Steps

The transfer function for this circuit is given below.

Equation 1. GUID-765A1511-1368-4125-8AC1-6D63477ED12F-low.gif

  1. Select a reasonable resistance value for R3.
    Equation 1. GUID-8E1D488C-B65C-455C-A194-98520DF7184F-low.gif
  2. Calculate gain required for Vi1. For this design, half of the output swing is devoted to each input.
    Equation 1. GUID-E44F9F92-1AE6-499E-9C28-06A96104F2BC-low.gif
  3. Calculate the value of R1.
    Equation 1. GUID-B92F22A3-787D-474E-8D7B-F88BF1DF1DAC-low.gif
  4. Calculate gain required for Vi2. For this design, half of the output swing is devoted to each input.
    Equation 1. GUID-D9750B33-E623-4548-95BF-24AF36DE21CD-low.gif
  5. Calculate the value of R2.
    Equation 1. GUID-9F73CC67-8F3A-4920-A98E-6080F1CE26A8-low.gif
  6. Calculate the small signal circuit bandwidth to ensure it meets the 10-kHz requirement. Be sure to use the noise gain (NG), or non-inverting gain, of the circuit. When calculating the noise gain note that R1 and R2 are in parallel.
    Equation 1. GUID-6EE7842D-E3D9-408A-BFFF-1DA6B0F0056D-low.gif
    Equation 1. GUID-1CC02DAE-51D0-499A-ABEE-1EBA664A6D4D-low.gif
    Equation 2. GUID-50CA6AF5-5E3F-4EF5-99D2-C8AB969D22D1-low.gif
    • This requirement is met because the closed-loop bandwidth is 102kHz and the design goal is 10kHz.
  7. Calculate the minimum slew rate to minimize slew-induced distortion.
    Equation 3. GUID-4FA40CD7-2A8C-445B-9C54-159582F62622-low.gif
    Equation 3. GUID-982A10C7-D908-4AFA-9C24-8B57F64FDD50-low.gif
    • SROPA170=0.4V/µs, therefore it meets this requirement.
  8. To avoid stability issues ensure that the zero created by the gain setting resistors and input capacitance of the device is greater than the bandwidth of the circuit.
    Equation 4. GUID-8AB7D367-130F-4971-8E34-78124300AC86-low.gif
    Equation 4. GUID-5ED77236-4FE4-43C9-A2DD-541DAB3796A0-low.gif
    Equation 5. GUID-0AFFCB09-03EA-43B8-97E4-9D75DA5AF754-low.gif
    • Ccm and Cdiff are the common-mode and differential input capacitances.
    • Since the zero frequency is greater than the bandwidth of the circuit, this requirement is met.

Design Simulations

DC Simulation Results

This simulation sweeps Vi1 from –2.5V to 2.5V while Vi2 is held constant at 0V. The output is inverted and ranges from –2.44V to 2.44V.

GUID-DD97BAD5-A640-490A-A029-E6B8A5D222C9-low.gif

This simulation sweeps Vi2 from –250mV to 250mV while Vi1 is held constant at 0V. The output is inverted and ranges from –2.44V to 2.44V.

GUID-CDFA6984-C77D-4EC5-87F8-13D09AE36A96-low.gif

AC Simulation Results

This simulation shows the bandwidth of the circuit. Note that the bandwidth is the same for either input. This is because the bandwidth depends on the noise gain of the circuit, not the signal gain of each input. These results correlate well with the calculations.

GUID-9FB0378E-4EAC-497A-9981-D848B080FE9B-low.gif

Transient Simulation Results

This simulation shows the inversion and summing of the two input signals. Vi1 is a 1-kHz, 5-Vpp sine wave and Vi2 is a 10-kHz, 500-mVpp sine wave. Since both inputs are properly amplified or attenuated, the output is within specification.

GUID-330A37F4-210B-48F0-8D8A-8B7A7FB21595-low.gif

Design References

See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.

See circuit SPICE simulation file SBOC494.

For more information on many op amp topics including common-mode range, output swing, bandwidth, and how to drive an ADC please visit TI Precision Labs.

Design Featured Op Amp

OPA170
Vss 2.7V to 36V
VinCM (Vee-0.1V) to (Vcc-2V)
Vout Rail-to-rail
Vos 0.25mV
Iq 110µA
Ib 8pA
UGBW 1.2MHz
SR 0.4V/µs
#Channels 1, 2, 4
www.ti.com/product/opa170

Design Alternate Op Amp

LMC7101
Vss 2.7V to 15.5V
VinCM Rail-to-rail
Vout Rail-to-rail
Vos 110µV
Iq 0.8mA
Ib 1pA
UGBW 1.1MHz
SR 1.1V/µs
#Channels 1
www.ti.com/product/lmc7101
Revision History
Revision Date Change
C January 2021 Updated Formula format
B December 2020 Updated Design Goals Table
A January 2019 Down-style title.
Updated title role to Amplifiers.
Added link to circuit cookbook landing page.