SCPS193D
July 2010 – January 2023
TCA6424A
PRODUCTION DATA
1
Features
2
Description
3
Revision History
4
Description (continued)
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings (1)
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
I2C Interface Timing Requirements
6.7
Reset Timing Requirements
6.8
Switching Characteristics
6.9
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.1.1
Voltage Translation
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
I/O Port
8.3.2
I2C Interface
8.4
Device Functional Modes
8.4.1
Device Address
8.5
Programming
8.5.1
Power-On Reset
8.5.2
Reset Input ( RESET)
8.5.3
Interrupt Output ( INT)
8.5.4
Bus Transactions
8.5.4.1
Writes
8.5.4.2
Reads
8.6
Register Maps
8.6.1
Control Register and Command Byte
8.6.2
Register Descriptions
9
Application and Implementation
9.1
Typical Application
9.1.1
Detailed Design Procedure
9.1.1.1
Minimizing ICC When I/Os Control LEDs
9.2
Power Supply Recommendation
10
Device and Documentation Support
10.1
Receiving Notification of Documentation Updates
10.2
Support Resources
10.3
Trademarks
10.4
Electrostatic Discharge Caution
10.5
Glossary
Mechanical, Packaging, and Orderable Information
1
Features
Operating power-supply voltage range of 1.65 V to 5.5 V
Allows bidirectional voltage-level translation and GPIO expansion between:
1.8-V SCL/SDA and
1.8-V, 2.5-V, 3.3-V, or 5-V P Port
2.5-V SCL/SDA and
1.8-V, 2.5-V, 3.3-V, or 5-V P Port
3.3-V SCL/SDA and
1.8-V, 2.5-V, 3.3-V, or 5-V P Port
5-V SCL/SDA and
1.8-V, 2.5-V, 3.3-V, or 5-V P Port
I
2
C to Parallel port expander
Low standby current consumption of 1 μA
Schmitt-Trigger action allows slow input transition and better switching noise immunity at the SCL and SDA inputs
V
hys
= 0.18 V Typ at 1.8 V
V
hys
= 0.25 V Typ at 2.5 V
V
hys
= 0.33 V Typ at 3.3 V
V
hys
= 0.5 V Typ at 5 V
5-V Tolerant I/O ports
Active-low reset input (
RESET
)
Open-drain active-low interrupt output (
INT
)
400-kHz Fast I
2
C Bus
Input/output configuration register
Polarity inversion register
Internal power-on reset
Power up with all channels configured as inputs
No glitch on power up
Noise filter on SCL/SDA inputs
Latched outputs with high-current drive maximum capability for directly driving LEDs
Latch-up performance exceeds 100 mA per JESD 78, class II
ESD protection exceeds JESD 22
2000-V Human-body model (A114-A)
200-V Machine model (A115-A)
1000-V Charged-device model (C101)
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