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DP83TC812-Q1 TC10 System Timing Measurements
SNLA417
January 2023
DP83TC812R-Q1
,
DP83TC812S-Q1
CONTENTS
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DP83TC812-Q1 TC10 System Timing Measurements
Abstract
1
Introduction
1.1
Acronyms
2
TC10 Test Setup
2.1
Overview
2.2
Wakeup to Linking Sequence
3
Measurement Summary
3.1
Complete Timing Diagram
3.2
Measurement Summary
3.3
LP1 Wake to Linking Time
4
Timing Measurements
4.1
LP1 WAKE to INH (T1)
4.2
LP1 INH to WUP (T2)
4.3
WUP to PHY INH (T3)
4.4
PHY INH/Buck EN to Buck nRESET (T4)
4.5
Buck nRESET/PMIC Enable to MCU nReset (T5)
4.6
MCU nReset to MDIO Communication (T6 and T7)
4.7
MDIO Master Configuration + Linking (T8 and T9)
5
Measurement Evaluation
5.1
Recommendations for Optimizing Variable TC10 Times
5.1.1
Improving MCU Boot-up Time (T6)
5.1.2
Improving MDIO State Machine (T7)
5.1.3
Optimizing MDIO Timeline (T8)
5.1.3.1
Optimizing Master Configuration by Removing Polling
5.1.3.2
Optimizing Master Configuration by Improving MDC
5.1.4
PHY Configuration During Sleep
5.1.5
Other Configurable Values
5.2
Alternative TC10 Test
6
Conclusion
7
References
IMPORTANT NOTICE
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