SCES382M
March 2002 – August 2022
SN74AUC1G125
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics: CL = 15 pF
6.7
Switching Characteristics: CL = 30 pF
6.8
Operating Characteristics
6.9
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
ULTTL CMOS Outputs
8.3.2
Standard CMOS Inputs
8.3.3
Partial Power Down (Ioff)
8.3.4
Clamp Diode Structure
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
Support Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DCK|5
MPDS025J
YZP|5
MXBG018L
DBV|5
MPDS018T
Thermal pad, mechanical data (Package|Pins)
Orderable Information
sces382m_oa
sces382m_pm
1
Features
Optimized for 1.8-V operation
±8-mA output drive at 1.8 V
Maximum t
pd
of 2.5 ns at 1.8 V, 30 pF load
Wide operating voltage range of 0.8 V to 2.7 V
Over-voltage tolerant I/Os support up to 3.6 V, independent of V
CC
Available in the Texas Instruments
NanoFree™
package
I
off
feature supports partial power down mode and back drive protection
Low power consumption, 10-µA maximum I
CC
Latch-up performance exceeds 100 mA per JESD 78, Class II
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