SCES878 March   2019 SN74AXCH4T245

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Functional Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics, VCCA = 0.7 ± 0.05 V
    7. 6.7  Switching Characteristics, VCCA = 0.8 ± 0.04 V
    8. 6.8  Switching Characteristics, VCCA = 0.9 ± 0.045 V
    9. 6.9  Switching Characteristics, VCCA = 1.2 ± 0.1 V
    10. 6.10 Switching Characteristics, VCCA = 1.5 ± 0.1 V
    11. 6.11 Switching Characteristics, VCCA = 1.8 ± 0.15 V
    12. 6.12 Switching Characteristics, VCCA = 2.5 ± 0.2 V
    13. 6.13 Switching Characteristics, VCCA = 3.3 ± 0.3 V
    14. 6.14 Operating Characteristics: TA = 25°C
    15. 6.15 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Load Circuit and Voltage Waveforms
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Standard CMOS Inputs
      2. 8.3.2  Balanced High-Drive CMOS Push-Pull Outputs
      3. 8.3.3  Partial Power Down (Ioff)
      4. 8.3.4  VCC Isolation
      5. 8.3.5  Over-voltage Tolerant Inputs
      6. 8.3.6  Glitch-free Power Supply Sequencing
      7. 8.3.7  Negative Clamping Diodes
      8. 8.3.8  Fully Configurable Dual-Rail Design
      9. 8.3.9  Supports High-Speed Translation
      10. 8.3.10 Bus-Hold Data Inputs
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Fully configurable dual-rail design allows each port to operate with a power supply range from 0.65 V to 3.6 V
  • Bus-hold on data inputs eliminates the need for external pullup or pulldown resistors
  • Operating temperature from –40°C to +125°C
  • Multiple direction control pins to allow simultaneous up and down translation
  • Glitch-free power supply sequencing
  • Up to 380 Mbps support when translating from 1.8 V to 3.3 V
  • VCC isolation feature
    • Ioff supports partial-power-down mode operation
    • Compatible with AVC family level shifters
    • Latch-up performance exceeds 100 mA per JESD 78, Class II
    • ESD protection exceeds JESD 22
      • 8000-V Human-body model
      • 1000-V Charged-device model
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