SCDS167A May   2004  – July 2022 SN74CB3Q16211

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Electrical Characteristics
    5. 7.5 Switching Characteristics
    6. 7.6 Typical Characteristics
  8. Parameter Measurement Information
  9. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • Member of the Texas Instruments
    Widebus® family
  • High-bandwidth data path (up to 500 MHz(1))
  • 5-V tolerant I/Os with device powered up or powered down
  • Low and flat ON-state resistance (ron) characteristics over operating range
    (ron = 5 Ω typical)
  • Rail-to-rail switching on data I/O ports
    • 0-V to 5-V switching with 3.3-V VCC
    • 0-V to 3.3-V switching with 2.5-V VCC
  • Bidirectional data flow, with near-zero propagation delay
  • Low input or output capacitance minimizes loading and signal distortion
    (Cio(OFF) = 4 pF typical)
  • Fast switching frequency (fOE = 20 MHz maximum)
  • Data and control inputs provide undershoot clamp diodes
  • Low power consumption (ICC = 1 mA typical)
  • VCC operating range from 2.3 V to 3.6 V
  • Data I/Os support 0-V to 5-V signaling levels
    (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5 V)
  • Control inputs can be driven by TTL or
    5-V/3.3-V CMOS outputs
  • Ioff supports partial-power-down mode operation
  • Latch-up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports both digital and analog applications: PCI interface, differential signal interface, memory interleaving, bus isolation, low-distortion signal gating (1)
GUID-3893ADB8-D6BF-4A49-891F-3AC425414B1B-low.gif
† EN is the internal enable signal applied to the switch.
Simplified Schematic, Each FET Switch (SW)
For additional information regarding the performance characteristics of the CB3Q family, refer to the TI application report, CBT-C, CB3T, and CB3Q Signal-Switch Families.