SCLS985 January   2024 SN74LV4T125-EP

PRODUCTION DATA  

1.   1
2. 1 Features
3. 2 Applications
4. 3 Description
5. 4 Additional Product Selection
6. 5 Pin Configuration and Functions
7. 6 Specifications
   1. 6.1 Absolute Maximum Ratings
   2. 6.2 ESD Ratings
   3. 6.3 Recommended Operating Conditions
   4. 6.4 Thermal Information
   5. 6.5 Electrical Characteristics
   6. 6.6 Switching Characteristics
   7. 6.7 Noise Characteristics
   8. 6.8 Typical Characteristics
8. 7 Parameter Measurement Information
9. 8 Detailed Description
   1. 8.1 Overview
   2. 8.2 Functional Block Diagram
   3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS 3-State Outputs
      2. 8.3.2 Clamp Diode Structure
      3. 8.3.3 LVxT Enhanced Input Voltage
         1. 8.3.3.1 Down Translation
         2. 8.3.3.2 Up Translation
   4. 8.4 Device Functional Modes
10. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
       1. 9.2.1 Design Requirements
       2. 9.2.2 Detailed Design Procedure
       3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
       1. 9.4.1 Layout Guidelines
       2. 9.4.2 Layout Example
11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
12. 11Revision History
13. 12Mechanical, Packaging, and Orderable Information

SN74LV4T125-EP Single Power Supply Quadruple Buffer Translator GATE With 3-State Output CMOS Logic Level Shifter