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SN74LV4T125 Single Power Supply Quadruple Buffer Translator GATE With 3-State Output CMOS Logic Level Shifter
SCLS749C
February 2014 – June 2022
SN74LV4T125
PRODUCTION DATA
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SN74LV4T125 Single Power Supply Quadruple Buffer Translator GATE With 3-State Output CMOS Logic Level Shifter
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics
6.7
Noise Characteristics
6.8
Operating Characteristics
6.9
Typical Characteristics
7
Parameter Measurement Information
7.1
18
8
Detailed Description
8.1
Overview
8.1.1
Translating Down
8.1.2
Translating Up
8.2
Functional Block Diagram
8.3
Feature Description
8.4
Device Functional Modes
9
Applications and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Additional Product Selection
12.2
Receiving Notification of Documentation Updates
12.3
Support Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
PW|14
MPDS360A
RGY|14
MPQF114H
Thermal pad, mechanical data (Package|Pins)
RGY|14
QFND039Q
Orderable Information
scls749c_oa
scls749c_pm
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