SCLS949 august   2023 SN74LV595B-EP

PRODUCTION DATA  

1.   1
2. 1 Features
3. 2 Applications
4. 3 Description
5. 4 Revision History
6. 5 Pin Configuration and Functions
7. 6 Specifications
   1. 6.1  Absolute Maximum Ratings
   2. 6.2  ESD Ratings
   3. 6.3  Recommended Operating Conditions
   4. 6.4  Thermal Information
   5. 6.5  Electrical Characteristics
   6. 6.6  Timing Requirements, VCC = 2.5 V ± 0.2 V
   7. 6.7  Timing Requirements, VCC = 3.3 V ± 0.3 V
   8. 6.8  Timing Requirements, VCC = 5 V ± 0.5 V
   9. 6.9  Switching Characteristics, VCC = 2.5 V ± 0.2 V
   10. 6.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V
   11. 6.11 Switching Characteristics, VCC = 5 V ± 0.5 V
   12. 6.12 Noise Characteristics
   13. 6.13 Operating Characteristics
   14. 6.14 Typical Characteristics
8. 7 Parameter Measurement Information
9. 8 Detailed Description
   1. 8.1 Overview
   2. 8.2 Functional Block Diagram
   3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS 3-State Outputs
      2. 8.3.2 Latching Logic
      3. 8.3.3 Partial Power Down (Ioff)
      4. 8.3.4 Clamp Diode Structure
   4. 8.4 Device Functional Modes
10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
       1. 9.2.1 Power Considerations
       2. 9.2.2 Input Considerations
       3. 9.2.3 Output Considerations
       4. 9.2.4 Detailed Design Procedure
       5. 9.2.5 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
       1. 9.4.1 Layout Guidelines
       2. 9.4.2 Layout Example
11. 10Device and Documentation Support
    1. 10.1 Documentation Support
       1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
12. 11Mechanical, Packaging, and Orderable Information

SN74LV595B-EP Enhanced Product, 2-V to 5.5-V, Low-Noise, 8-bit Shift Register With
3-State Outputs