SCES939
April 2022
SN74LXCH1T45
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics, VCCA = 1.2 ± 0.1 V
6.7
Switching Characteristics, VCCA = 1.5 ± 0.1 V
6.8
Switching Characteristics, VCCA = 1.8 ± 0.15 V
6.9
Switching Characteristics, VCCA = 2.5 ± 0.2 V
6.10
Switching Characteristics, VCCA = 3.3 ± 0.3 V
6.11
Switching Characteristics, VCCA = 5.0 ± 0.5 V
6.12
Switching Characteristics: Tsk, TMAX
6.13
Operating Characteristics
6.14
Typical Characteristics
7
Parameter Measurement Information
7.1
Load Circuit and Voltage Waveforms
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
CMOS Schmitt-Trigger Inputs
8.3.1.1
Control Inputs with Integrated Static Pull-Down Resistors
8.3.2
Balanced High-Drive CMOS Push-Pull Outputs
8.3.3
Partial Power Down (Ioff)
8.3.4
VCC Isolation and VCC Disconnect
8.3.5
Over-Voltage Tolerant Inputs
8.3.6
Glitch-Free Power Supply Sequencing
8.3.7
Negative Clamping Diodes
8.3.8
Fully Configurable Dual-Rail Design
8.3.9
Supports High-Speed Translation
8.3.10
Bus-Hold Data Inputs
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Enable Times
9.3
Typical Application
9.3.1
Design Requirements
9.3.2
Detailed Design Procedure
9.3.3
Application Curve
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
Support Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DRY|6
MPDS221F
DCK|6
MPDS114E
DTQ|6
MUSS003A
Thermal pad, mechanical data (Package|Pins)
DRY|6
QFND138E
Orderable Information
sces939_oa
sces939_pm
1
Features
Fully configurable dual-rail design allows each port to operate from 1.1 V to 5.5 V
Robust, glitch-free power supply sequencing
Up to 420-Mbps support for 3.3 V to 5.0 V
Bus hold
on data inputs eliminates the need for external pull-up and pull-down resistors
Schmitt-trigger control inputs allow for slow or noisy inputs
Control inputs with integrated static pull-down resistors
allow for floating control inputs
High drive strength (up to 32 mA at 5 V)
Low power consumption
3-µA maximum (25°C)
6-µA maximum (–40°C to 125°C)
V
CC
isolation and V
CC
disconnect
feature
If either V
CC
supply is < 100 mV all I/O's become high-impedance
I
off-float
supports V
CC
disconnect operation
I
off
supports partial-power-down mode operation
Compatible with LVC family level shifters
Control logic (DIR) are referenced to V
CCA
Operating temperature from –40°C to +125°C
Latch-up performance exceeds 100 mA per JESD 78, class II
ESD protection exceeds JESD 22
4000-V human-body model
1000-V charged-device model
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