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TCAN4550-Q1 Automotive Controller Area Network Flexible Data Rate (CAN FD) System Basis Chip with Integrated Controller and Transceiver
SLLSEZ5D
January 2018 – June 2022
TCAN4550-Q1
PRODUCTION DATA
CONTENTS
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TCAN4550-Q1 Automotive Controller Area Network Flexible Data Rate (CAN FD) System Basis Chip with Integrated Controller and Transceiver
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specification
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
ESD Ratings, IEC ESD and ISO Transient Specification
6.4
Recommended Operating Conditions
6.5
Thermal Information
6.6
Supply Characteristics
6.7
Electrical Characteristics
6.8
Timing Requirements
6.9
Switching Characteristics
6.10
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
VSUP Pin
8.3.2
VIO Pin
8.3.3
VCCOUT Pin
8.3.4
GND
8.3.5
INH Pin
8.3.6
WAKE Pin
8.3.7
FLTR Pin
8.3.8
RST Pin
8.3.9
OSC1 and OSC2 Pins
8.3.10
nWKRQ Pin
8.3.11
nINT Interrupt Pin
8.3.12
GPIO1 Pin
8.3.13
GPO2 Pin
8.3.14
CANH and CANL Bus Pins
8.4
Device Functional Modes
8.4.1
Normal Mode
8.4.2
Standby Mode
8.4.3
Sleep Mode
8.4.3.1
Bus Wake via RXD_INT Request (BWRR) in Sleep Mode
8.4.3.2
Local Wake-Up (LWU) via WAKE Input Terminal
8.4.4
Test Mode
8.4.5
Failsafe Feature
8.4.6
Protection Features
8.4.6.1
Watchdog Function
8.4.6.2
Driver and Receiver Function
8.4.6.3
Floating Terminals
8.4.6.4
TXD_INT Dominant Timeout (DTO)
8.4.6.5
CAN Bus Short Circuit Current Limiting
8.4.6.6
Thermal Shutdown
8.4.6.7
Under-Voltage Lockout (UVLO) and Unpowered Device
8.4.6.7.1
UVSUP and UVCCOUT
8.4.6.7.2
UVIO
8.4.6.7.3
Fault and M_CAN Core Behavior:
8.4.7
CAN FD
8.5
Programming
8.5.1
SPI Communication
8.5.1.1
Chip Select Not (nCS):
8.5.1.2
SPI Clock Input (SCLK):
8.5.1.3
SPI Data Input (SDI):
8.5.1.4
SPI Data Output (SDO):
8.5.2
Register Descriptions
8.6
Register Maps
8.6.1
Device ID and Interrupt/Diagnostic Flag Registers: 16'h0000 to 16'h002F
8.6.1.1
DEVICE_ID1[31:0] (address = h0000) [reset = h4E414354]
8.6.1.2
DEVICE_ID2[31:0] (address = h0004) [reset = h30353534]
8.6.1.3
Revision (address = h0008) [reset = h00110201]
8.6.1.4
Status (address = h000C) [reset = h0000000U]
8.6.1.5
SPI Error status mask (address = h0010) [reset = h00000000]
8.6.2
Device Configuration Registers: 16'h0800 to 16'h08FF
8.6.2.1
Modes of Operation and Pin Configuration Registers (address = h0800) [reset = hC8000468]
8.6.2.2
Timestamp Prescaler (address = h0804) [reset = h00000002]
8.6.2.3
Test Register and Scratch Pad (address = h0808) [reset = h00000000]
8.6.2.4
Test Register (address = h080C) [reset = h00000000]
8.6.3
Interrupt/Diagnostic Flag and Enable Flag Registers: 16'h0820/0824 and 16'h0830
8.6.3.1
Interrupts (address = h0820) [reset = h00100000]
8.6.3.2
MCAN Interrupts (address = h0824) [reset = h00000000]
8.6.3.3
Interrupt Enables (address = h0830 ) [reset = hFFFFFFFF]
8.6.4
CAN FD Register Set: 16'h1000 to 16'h10FF
8.6.4.1
Core Release Register (address = h1000) [reset = hrrrddddd]
8.6.4.2
Endian Register (address = h1004) [reset = h87654321]
8.6.4.3
Customer Register (address = h1008) [reset = h00000000]
8.6.4.4
Data Bit Timing & Prescaler (address = h100C) [reset = h0000A33]
8.6.4.5
Test Register (address = h1010 ) [reset = h00000000]
8.6.4.6
RAM Watchdog (address = h1014) [reset = h00000000]
8.6.4.7
Control Register (address = h1018) [reset = 0000 0019]
8.6.4.8
Nominal Bit Timing & Prescaler Register (address = h101C) [reset = h06000A03]
8.6.4.9
Timestamp Counter Configuration (address = h1020) [reset = h00000000]
8.6.4.10
Timestamp Counter Value (address = h1024) [reset = h00000000]
8.6.4.11
Timeout Counter Configuration (address = h1028) [reset = hFFFF0000]
8.6.4.12
Timeout Counter Value (address = h102C) [reset = h0000FFFF]
8.6.4.13
Reserved (address = h1030 - h103C) [reset = h00000000]
8.6.4.14
Error Counter Register (address = h1040) [reset = h00000000]
8.6.4.15
Protocol Status Register (address = h1044) [reset = h00000707]
8.6.4.16
Transmitter Delay Compensation Register (address = h1048) [reset = h00000000]
8.6.4.17
Reserved (address = h104C) [reset = h00000000]
8.6.4.18
Interrupt Register (address = h1050) [reset = h00000000]
8.6.4.19
Interrupt Enable (address = h1054) [reset = h00000000]
8.6.4.20
Interrupt Line Select (address = h1058) [reset = h00000000]
8.6.4.21
Interrupt Line Enable (address = h105C) [reset = h00000000]
8.6.4.22
Reserved (address = h1060 - h107C) [reset = h00000000]
8.6.4.23
Global Filter Configuration (address = h1080) [reset = h00000000]
8.6.4.24
Standard ID Filter Configuration (address = h1084) [reset = h00000000]
8.6.4.25
Extended ID Filter Configuration (address = h1088) [reset = h00000000]
8.6.4.26
Reserved (address = h108C) [reset = h00000000]
8.6.4.27
Extended ID AND Mask (address = h1090) [reset = h1FFFFFFF]
8.6.4.28
High Priority Message Status (address = h1094) [reset = h00000000]
8.6.4.29
New Data 1 (address = h1098) [reset = h00000000]
8.6.4.30
New Data 2 (address = h109C) [reset = h00000000]
8.6.4.31
Rx FIFO 0 Configuration (address = h10A0) [reset = h00000000]
8.6.4.32
Rx FIFO 0 Status (address = h10A4) [reset = h00000000]
8.6.4.33
Rx FIFO 0 Acknowledge (address = h10A8) [reset = h00000000]
8.6.4.34
Rx Buffer Configuration (address = h10AC) [reset = h00000000]
8.6.4.35
Rx FIFO 1 Configuration (address = h10B0) [reset = h00000000]
8.6.4.36
Rx FIFO 1 Status (address = h10B4) [reset = h00000000]
8.6.4.37
Rx FIFO 1 Acknowledge (address = h10B8) [reset = h00000000]
8.6.4.38
Rx Buffer/FIFO Element Size Configuration (address = h10BC) [reset = h00000000]
8.6.4.39
Tx Buffer Configuration (address = h10C0) [reset = h00000000]
8.6.4.40
Tx FIFO/Queue Status (address = h10C4) [reset = h00000000]
8.6.4.41
Tx Buffer Element Size Configuration (address = h10C8) [reset = h00000000]
8.6.4.42
Tx Buffer Request Pending (address = h10CC) [reset = h00000000]
8.6.4.43
Tx Buffer Add Request (address = h10D0) [reset = h00000000]
8.6.4.43.1
Tx Buffer Cancellation Request (address = h10D4 [reset = h00000000]
8.6.4.43.2
Tx Buffer Add Request Transmission Occurred (address = h10D8) [reset = h00000000]
8.6.4.43.3
Tx Buffer Cancellation Finished (address = h10DC) [reset = h00000000]
8.6.4.43.4
Tx Buffer Transmission Interrupt Enable (address = h10E0) [reset = h00000000]
8.6.4.43.5
Tx Buffer Cancellation Finished Interrupt Enable (address = h10E4) [reset = h00000000]
8.6.4.43.6
Reserved (address = h10E8) [reset = h00000000]
8.6.4.43.7
Reserved (address = h10EC) [reset = h00000000]
8.6.4.43.8
Tx Event FIFO Configuration (address = h10F0) [reset = h00000000]
8.6.4.43.9
Tx Event FIFO Status (address = h10F4) [reset = h00000000]
8.6.4.43.10
Tx Event FIFO Acknowledge (address = h10F8) [reset = h00000000]
8.6.4.43.11
Reserved (address = h10FC) [reset = h00000000]
9
Application and Implementation
9.1
Application Design Consideration
9.1.1
Crystal and Clock Input Requirements
9.1.2
Bus Loading, Length and Number of Nodes
9.1.3
CAN Termination
Termination
9.1.3.1
CAN Bus Biasing
9.1.4
INH Brownout Behavior
9.2
Typical Application
9.2.1
Detailed Requirements
9.2.2
Detailed Design Procedures
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.1.1.1
CAN Transceiver Physical Layer Standards:
12.1.1.2
EMC requirements:
12.1.1.3
Conformance Test requirements:
12.1.1.4
Support Documents
12.2
Receiving Notification of Documentation Updates
12.3
Support Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
RGY|20
MPQF116H
Thermal pad, mechanical data (Package|Pins)
RGY|20
QFND734
Orderable Information
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sllsez5d_pm
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