THS4281 Very Low-Power, High-Speed, Rail-to-Rail Input and Output Voltage-Feedback Operational Amplifier

1 Features

• Very Low Quiescent Current: 750 μA (at 5 V)
• Rail-to-Rail Input and Output:
  • Common-Mode Input Voltage Extends
    400 mV Beyond the Rails
  • Output Swings Within 150 mV From the Rails
• Wide –3-dB Bandwidth at 5 V:
  • 90 MHz at Gain = +1, 40 MHz at Gain = +2
• High Slew Rate: 35 V/μs
• Fast Settling Time (2-V Step):
  • 78 ns to 0.1%
  • 150 ns to 0.01%
• Low Distortion at Gain = +2, V_O = 2-V_PP, 5 V:
  • –91 dBc at 100 kHz, –67 dBc at 1 MHz
• Input Offset Voltage: 2.5 mV (Max at +25°C)
• Output Current > 30 mA (10-Ω Load, 5 V)
• Low Voltage Noise of 12.5 nV/√Hz
• Supply Voltages: +2.7 V, 3 V, +5 V, ±5 V, +15 V
• Packages: SOT23, MSOP, and SOIC

2 Applications

• Portable/Battery-Powered Applications
• High Channel Count Systems
• ADC Buffer
• Active Filters
• Current Sensing

3 Description

Fabricated using the BiCom-II process, the THS4281 is a low-power, rail-to-rail input and output, voltage-feedback operational amplifier designed to operate over a wide power-supply range of 2.7-V to 15-V single supply, and ±1.35-V to ±7.5-V dual supply. Consuming only 750 μA with a unity gain bandwidth of 90 MHz and a high 35-V/μs slew rate, the THS4281 allows portable or other power-sensitive applications to realize high performance with minimal power. To ensure long battery life in portable applications, the quiescent current is trimmed to be less than 900 μA at +25°C, and 1 mA from –40°C to +85°C.

The THS4281 is a true single-supply amplifier with a specified common-mode input range of 400 mV beyond the rails. This allows for high-side current sensing applications without phase reversal concerns. Its output swings to within 40 mV from the rails with 10-kΩ loads, and 150 mV from the rails with 1-kΩ loads.

The THS4281 has a good 0.1% settling time of 78 ns, and 0.01% settling time of 150 ns. The low THD of –87 dBc at 100 kHz, coupled with a maximum offset voltage of less than 2.5 mV, makes the THS4281 a good match for high-resolution ADCs sampling less than 2 MSPS.

The THS4281 is offered in a space-saving SOT23-5 package, a small MSOP-8 package, and the industry standard SOIC-8 package.

1. For all available packages, see the orderable addendum at the end of the data sheet.

High-side, Low Power Current-Sensing system

4 Revision History

Changes from A Revision (November 2009) to B Revision

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
• Removed the Packaging/Ordering Information table Go
• Removed Design Tools section Go
• Updated Thermal Values Go
• Removed the Applications Section Contents section Go
• Removed the Bill of Materials section Go

Changes from * Revision (April 2004) to A Revision

• Updated document format to current standardsGo
• Deleted Lead temperature specification from Absolute Maximum Ratings tableGo
• Revised Driving Capacitive Loads sectionGo
• Changed Board Layout section; revised statements in fourth recommendation about how to make connections to other wideband devices on the boardGo

5 Pin Configuration and Functions

D and DGK Packages

8-Pin SOIC

Top View

DBV Package

5-Pin SOT-23

Top View

NOTE:

NC Indicates there is no internal connection to these pins

6 Specifications

6.9 Typical Characteristics

Figure 1. Quiescent Current vs Supply Voltage

VS = ±5 V

Figure 3. Input Offset Voltage vs Common-Mode Input Voltage

Figure 5. Positive Voltage Headroom vs Source Current

VS = 5 V

Figure 7. Output Voltage vs Load Resistance

VS = 15 V)

Figure 9. Output Voltage vs Load Resistance

VS = 2.7 V

Figure 11. Frequency Response

VS = 5 V

Figure 13. Frequency Response

VS = 2.7 V

VS = 3 V

Figure 15. 0.1-dB Frequency Response

VS = 2.7 V

Figure 17. Frequency Response

VS = 5 V

Figure 19. Frequency Response

VS = 15 V

Figure 21. Frequency Response

VS = 5 V

Figure 23. Large-Signal Frequency Response

Figure 25. Open-Loop Gain vs Frequency

Figure 27. Rejection Ratio vs Frequency

VS = 2.7 V

Figure 29. Slew Rate

VS = ±5 V

Figure 31. Slew Rate

VS = ±1.35 V

Figure 33. Settling Time

VS = ±2.5 V

Figure 35. Settling Time

VS = ±5 V

Figure 37. Settling Time

Gain = +1

Figure 39. Harmonic Distortion vs Frequency

VS = 3 V, 3.3 V

Figure 41. Harmonic Distortion vs Frequency

Gain = +2

Figure 43. Harmonic Distortion vs Frequency

\

VS = 2.7 V, 5 V

Figure 45. Harmonic Distortion vs Output Voltage

VS = 3.3 V, 15 V

Figure 47. Harmonic Distortion vs Output Voltage

VS = 3 V

Figure 49. Total Harmonic Distortion + Noise vs Frequency

VS = ±5 V

Figure 51. Total Harmonic Distortion + Noise vs Frequency

f = 1 kHz

Figure 53. Total Harmonic Distortion + Noise vs Output Voltage

f = 100 kHz

Figure 55. Total Harmonic Distortion + Noise vs Output Voltage

VS = 5 V

Figure 57. Differential Phase vs Number of Loads

VS = ±5 V

Figure 59. Differential Phase vs Number of Loads

VS = 5 V

Figure 61. Input Bias and Offset Current vs Temperature

Figure 63. Small-Signal Transient Response

VS = 5 V

Figure 65. Overdrive Recovery Time

Figure 67. Overdrive Response Output Voltage vs Time

VS = 3 V

VS = 5 V

Figure 2. Input Offset Voltage vs Common-mode Input Voltage

VS = 15 V

Figure 4. Input Offset Voltage vs Common-Mode Input Voltage

Figure 6. Negative Voltage Headroom vs Sink Current

VS = ±5 V

Figure 8. Output Voltage vs Load Resistance

Figure 10. Frequency Response

VS = 3 V

Figure 12. Frequency Response

VS = ±5 V

Figure 14. Frequency Response

VS = 5 V, ±5 V, 15 V

Figure 16. 0.1-dB Frequency Response

VS = 3 V

Figure 18. Frequency Response

VS = ±5 V

Figure 20. Frequency Response

VS = 2.7 V

Figure 22. Large-Signal Frequency Response

VS = ±5 V

Figure 24. Large-Signal Frequency Response

Figure 26. Output Impedance vs Frequency

Figure 28. Noise vs Frequency

VS = 5 V

Figure 30. Slew Rate

VS = 15 V

Figure 32. Slew Rate

VS = ±1.35 V

Figure 34. Settling Time

VS = ±2.5 V

Figure 36. Settling Time

VS = ±5 V

Figure 38. Settling Time

Gain = +1

Figure 40. Harmonic Distortion vs Frequency

Gain = +2

Figure 42. Harmonic Distortion vs Frequency

Figure 44. Harmonic Distortion vs Load Resistance

VS = 3 V, ±5 V

Figure 46. Harmonic Distortion vs Output Voltage

VS = 2.7 V

Figure 48. Total Harmonic Distortion + Noise vs Frequency

VS = 5 V

Figure 50. Total Harmonic Distortion + Noise vs Frequency

VS = 15 V

Figure 52. Total Harmonic Distortion + Noise vs Frequency

f = 10 kHz

Figure 54. Total Harmonic Distortion + Noise vs Output Voltage

VS = 5 V

Figure 56. Differential Gain vs Number of Loads

VS = ±5 V

Figure 58. Differential Gain vs Number of Loads

Figure 60. Input Offset Voltage vs Temperature

VS = 15 V

Figure 62. Input Bias and Offset Current vs Temperature

Figure 64. Large-Signal Transient Response

VS = ±5 V

Figure 66. Overdrive Recovery Time

7 Detailed Description

7.2 Feature Description

7.2.1 Wideband, Noninverting Operation

Figure 68 shows the noninverting gain configuration of 2 V/V used to demonstrate the typical performance curves.

Voltage feedback amplifiers can use a wide range of resistors values to set their gain with minimal impact on frequency response. Larger-valued resistors decrease loading of the feedback network on the output of the amplifier, but may cause peaking and instability. For a gain of +2, feedback resistor values between 1 kΩ and 4 kΩ are recommended for most applications. However, as the gain increases, the use of even higher feedback resistors can be used to conserve power. This is due to the inherent nature of amplifiers becoming more stable as the gain increases, at the expense of bandwidth. Figure 73 and Figure 74 show the THS4281 using feedback resistors of 10 kΩ and 100 kΩ. Be cautioned that using such high values with high-speed amplifiers is not typically recommended, but under certain conditions, such as high gain and good high-speed printed circuit board (PCB) layout practices, such resistances can be used.

Figure 68. Wideband, Noninverting Gain Configuration

7.2.2 Wideband, Inverting Operation

Figure 69 shows a typical inverting configuration where the input and output impedances and noise gain from Figure 68 are retained with an inverting circuit gain of –1 V/V.

Figure 69. Wideband, Inverting Gain Configuration

In the inverting configuration, some key design considerations must be noted. One is that the gain resistor (R_g) becomes part of the signal channel input impedance. If the input impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twisted pair, long PCB trace, or other transmission line conductors), R_g may be set equal to the required termination value and R_f adjusted to give the desired gain. However, care must be taken when dealing with low inverting gains, as the resulting feedback resistor value can present a significant load to the amplifier output. For example, an inverting gain of 2, setting R_g to 49.9 Ω for input matching, eliminates the need for R_M but requires a 100-Ω feedback resistor. The 100-Ω feedback resistor, in parallel with the external load, causes excessive loading on the amplifier output. To eliminate this excessive loading, it is preferable to increase both R_g and R_f values, as shown in Figure 69, and then achieve the input matching impedance with a third resistor (R_M) to ground. The total input impedance is the parallel combination of R_g and R_M.

Another consideration in inverting amplifier design is setting the bias current cancellation resistor (R_T) on the noninverting input. If the resistance is set equal to the total dc resistance presented to the device at the inverting terminal, the output dc error (due to the input bias currents) is reduced to the input offset current multiplied by R_T. In Figure 69, the dc source impedance presented at the inverting terminal is 2.49 kΩ || (2.49 kΩ + 25.3 Ω) ≈ 1.24 kΩ. To reduce the additional high-frequency noise introduced by the resistor at the noninverting input, R_T is bypassed with a 0.1-μF capacitor to ground (C_T).