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THS4552 Dual-Channel, Low-Noise, Precision, 150-MHz, Fully Differential Amplifier
SBOS831B
December 2016 – June 2021
THS4552
PRODUCTION DATA
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THS4552 Dual-Channel, Low-Noise, Precision, 150-MHz, Fully Differential Amplifier
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics: (VS+) – (VS–) = 5 V
6.6
Electrical Characteristics: (VS+) – (VS–) = 3 V
6.7
Typical Characteristics: (VS+) – (VS–) = 5 V
6.8
Typical Characteristics: (VS+) – (VS–) = 3 V
6.9
Typical Characteristics: 3 V to 5 V Supply Range
7
Parameter Measurement Information
7.1
Example Characterization Circuits
7.2
Output Interface Circuit for DC-Coupled Differential Testing
7.3
Output Common-Mode Measurements
7.4
Differential Amplifier Noise Measurements
7.5
Balanced Split-Supply Versus Single-Supply Characterization
7.6
Simulated Characterization Curves
7.7
Terminology and Application Assumptions
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Differential Open-Loop Gain and Output Impedance
8.3.2
Setting Resistor Values Versus Gain
8.3.3
I/O Headroom Considerations
8.3.4
Output DC Error and Drift Calculations and the Effect of Resistor Imbalances
8.4
Device Functional Modes
8.4.1
Operation from Single-Ended Sources to Differential Outputs
8.4.1.1
AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversions
8.4.1.2
DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversions
8.4.2
Operation from a Differential Input to a Differential Output
8.4.2.1
AC-Coupled, Differential-Input to Differential-Output Design Issues
8.4.2.2
DC-Coupled, Differential-Input to Differential-Output Design Issues
8.4.3
Input Overdrive Performance
9
Application and Implementation
9.1
Application Information
9.1.1
Noise Analysis
9.1.2
Factors Influencing Harmonic Distortion
9.1.3
Driving Capacitive Loads
9.1.4
Interfacing to High-Performance Precision ADCs
9.1.5
Operating the Power Shutdown Feature
9.1.6
Channel-to-Channel Crosstalk
9.1.7
Channel-to-Channel Mismatch
9.1.8
Designing Attenuators
9.1.9
The Effect of Adding a Feedback Capacitor
9.2
Typical Applications
9.2.1
An MFB Filter Driving an ADC Application
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.3
Application Curves
9.2.2
Differential Transimpedance Output to a High-Grade Audio PCM DAC Application
9.2.2.1
Design Requirements
9.2.2.2
Detailed Design Procedure
9.2.2.3
Application Curves
9.2.3
ADC3k Driver with a 2nd-Order RLC Interstage Filter Application
9.2.3.1
Design Requirements
9.2.3.2
Detailed Design Procedure
9.2.3.3
Application Curve
10
Power Supply Recommendations
10.1
Thermal Analysis
11
Layout
11.1
Layout Guidelines
11.1.1
Board Layout Recommendations
11.2
Layout Example
11.3
EVM Board
12
Device and Documentation Support
12.1
Device Support
12.1.1
TINA-TI Simulation Model Features
12.2
Documentation Support
12.2.1
Related Documentation
12.3
Receiving Notification of Documentation Updates
12.4
Support Resources
12.5
Trademarks
12.6
Electrostatic Discharge Caution
12.7
Glossary
13
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
PW|16
MPDS361A
RTW|24
MPQF167C
Thermal pad, mechanical data (Package|Pins)
RTW|24
QFND062N
Orderable Information
sbos831b_oa
sbos831b_pm
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