Output Series Resistors to Reduce Transmission-Line Reflection NoiseThe CY74FCT2543T octal latched transceiver contains two sets of eight D-type latches. Separate latch enable (LEAB\, LEBA\) and output enable (OEAB\, OEBA\) inputs permit each latch set to have independent control of inputting and outputting in either direction of data flow. For example, for data flow from A to B, the A-to-B enable (CEAB\) input must be low to enter data from A or to take data from B, as indicated in the function table. With CEAB\ low, a low signal on the A-to-B latch enable (LEAB\) input makes the A-to-B latches transparent; a subsequent low-to-high transition of LEAB\ puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB\ and OEAB\ both low, the 3-state B output buffers are active and reflect data present at the output of the A latches. Control of data from B to A is similar, but uses CEAB\, LEAB\, and OEAB\ inputs. On-chip termination resistors at the outputs reduce system noise caused by reflections. The CY74FCT2543T can replace the CY74FCT543T to reduce noise in an existing design.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | 8-Bit Latched Transceiver With 3-State Outputs datasheet (Rev. C) | 02 Nov 2001 | |
| Selection guide | Logic Guide (Rev. AB) | 12 Jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 Dec 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 Jan 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 Jul 2004 | ||
| Application note | Selecting the Right Level Translation Solution (Rev. A) | 22 Jun 2004 | ||
| User guide | CYFCT Parameter Measurement Information | 02 Apr 2001 | ||
| Selection guide | Advanced Bus Interface Logic Selection Guide | 09 Jan 2001 |
For additional terms or required resources, click any title below to view the detail page where available.
The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| SOIC (DW) | 24 | Ultra Librarian |
| SSOP (DBQ) | 24 | Ultra Librarian |
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