The LP2996A linear regulator is designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device also supports DDR2, DDR3 and DDR3L VTT bus termination with VDDQ min of 1.35V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2996A also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.
An additional feature found on the LP2996A is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | LP2996A DDR Termination Regulator datasheet | PDF | HTML | 27 Jun 2014 |
| Application note | Limiting DDR Termination Regulators’ Inrush Current | 23 Aug 2016 |
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The LP2998 evaluation board is designed to provide the design Engineer with a fully functional prototype system in which to evaluate the LP2998 in both a static environment and with a complete memory system.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| HSOIC (DDA) | 8 | Ultra Librarian |
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